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JPH0416767B2 - - Google Patents
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JPH0416767B2 - - Google Patents

Info

Publication number
JPH0416767B2
JPH0416767B2 JP57214114A JP21411482A JPH0416767B2 JP H0416767 B2 JPH0416767 B2 JP H0416767B2 JP 57214114 A JP57214114 A JP 57214114A JP 21411482 A JP21411482 A JP 21411482A JP H0416767 B2 JPH0416767 B2 JP H0416767B2
Authority
JP
Japan
Prior art keywords
ceramic
wafer
conductive layer
wafers
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57214114A
Other languages
Japanese (ja)
Other versions
JPS59104623A (en
Inventor
Hiroyuki Seto
Katsuhiko Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP21411482A priority Critical patent/JPS59104623A/en
Publication of JPS59104623A publication Critical patent/JPS59104623A/en
Publication of JPH0416767B2 publication Critical patent/JPH0416767B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/03Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect
    • G02F1/055Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect the active material being a ceramic
    • G02F1/0551Constructional details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) この発明はセラミツク素子の製造方法、特に、
透光性セラミツクウエハやアルミナウエハの両面
に相互に相対する多数の電極を形成してなる光シ
ヤツタその他の電極アレイを有するセラミツク素
子の製造方法に関する。
[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a method for manufacturing a ceramic element, in particular,
The present invention relates to a method of manufacturing a light shutter or other ceramic element having an electrode array, which is formed by forming a large number of mutually opposing electrodes on both sides of a translucent ceramic wafer or an alumina wafer.

(従来の技術) 一般に、電極アレイを有するセラミツク素子、
例えば、光シヤツタを製造する場合、シヤツタの
駆動電圧を低下させると共に、光学的均一性を向
上させるために、セラミツクウエハの両表面に表
裏相対する多数の電極を形成することが要求され
る。
(Prior Art) Generally, a ceramic element having an electrode array,
For example, when manufacturing an optical shutter, it is required to form a large number of opposing electrodes on both surfaces of a ceramic wafer in order to reduce the drive voltage of the shutter and improve optical uniformity.

(発明が解決しようとする課題) しかしながら、ウエハの両表面からワイヤーボ
ンデイングにより相互に独立した多数の電極を取
り出すことは、電極ピツチが数百μm以下と極め
て小さいことから非常に困難であり、また、ウエ
ハはその肉厚が薄くなる程破損し易くなることか
ら、量産は事実上不可能であつた。
(Problem to be Solved by the Invention) However, it is extremely difficult to extract a large number of mutually independent electrodes from both surfaces of a wafer by wire bonding because the electrode pitch is extremely small, several hundred μm or less. However, the thinner the wafer, the more easily it is damaged, making mass production virtually impossible.

従つて、本発明は、表裏相対する電極を相互に
接続した構造の電極アレイを有するセラミツク素
子を容易に、かつ、多量に生産することができる
方法を提供することを目的とする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method that can easily and in large quantities produce a ceramic element having an electrode array having a structure in which electrodes facing each other are connected to each other.

(課題を解決するための手段) 本発明は、前記課題を解決するための手段とし
て、セラミツクウエハの両表面に相対して形成さ
れた複数の電極をその端面に形成された導電部を
介して接続してなるセラミツク素子を製造するに
当たり、セラミツクウエハの両表面に複数の電極
を形成する前または形成した後、(イ)複数枚のセラ
ミツクウエハを積層して可燃性接合剤で密着固定
しブロツクとする工程と、(ロ)該ブロツクの端面に
その積層方向に伸張する多数の凹部を形成して各
セラミツクウエハの端面にその厚さ方向の凹部を
多数形成する工程と、(ハ)前記ブロツクの凹部を形
成した端面に導電性ペーストを塗布した後、これ
を焼成してセラミツクウエハ端面に導電層を形成
すると共に、個々のセラミツクウエハに分離する
工程と、(ニ)各セラミツクウエハの端面に形成され
た導電層のうち前記凹部以外の端面に形成された
導電層を除去する工程と、からなるセラミツク素
子の製造方法を提供するものである。
(Means for Solving the Problems) As a means for solving the above problems, the present invention provides a method for connecting a plurality of electrodes formed facing each other on both surfaces of a ceramic wafer via conductive parts formed on the end faces thereof. In manufacturing a connected ceramic element, before or after forming a plurality of electrodes on both surfaces of a ceramic wafer, (a) a plurality of ceramic wafers are stacked and tightly fixed with a flammable bonding agent to form a block; (b) forming a large number of recesses extending in the stacking direction on the end face of each ceramic wafer, and (c) forming a large number of recesses in the thickness direction on the end face of each ceramic wafer; After applying a conductive paste to the end surface with the recess formed therein, the paste is fired to form a conductive layer on the end surface of the ceramic wafer, and the process of separating the ceramic wafers into individual ceramic wafers; The present invention provides a method for manufacturing a ceramic element, which comprises the step of removing the conductive layer formed on the end face other than the recessed portion of the formed conductive layer.

前記セラミツクウエハの両表面上には、前記導
電層の形成前若しくは形成後に、セラミツクウエ
ハの両表面に電極層を形成し、次いで、フオトリ
ソグラフイにより多数の電極が形成されるが、そ
の電極層の形成方法としては蒸着法、スパツタリ
ング法、イオンプレーテイング法など乾式薄膜形
成法を採用するのが好ましい。
Before or after the formation of the conductive layer, electrode layers are formed on both surfaces of the ceramic wafer, and then a large number of electrodes are formed by photolithography. It is preferable to employ a dry thin film forming method such as a vapor deposition method, a sputtering method, or an ion plating method.

可燃性接合剤としては、導電性ベーストを焼き
付けて導電層を形成する際、燃焼して消失するも
のであれば任意のものを採用でき、代表的なもの
としてワツクス等が挙げられる。
As the combustible bonding agent, any material can be used as long as it burns and disappears when the conductive base is baked to form the conductive layer, and typical examples include wax.

(作用) 本発明の方法は、多数のセラミツクウエハを積
層してワツクス等の可燃性接合剤で密着固定して
ブロツクとすることにより、セラミツクウエハ端
面への切削加工および導電ペーストの塗布等の作
業を容易にすると共に、加工時の破損を防止し、
また、セラミツクウエハを密着固定する手段とし
てワツクス等の可燃性接合剤を使用することによ
り、導電性ペースト塗布後の焼成により導電層の
形成と同時に個々のセラミツクウエハへの分離を
自動的に行なわせ、作業の単純化を図れるように
している。
(Function) The method of the present invention involves stacking a large number of ceramic wafers and tightly fixing them with a flammable bonding agent such as wax to form a block. and prevent damage during machining.
In addition, by using a flammable bonding agent such as wax as a means of closely fixing the ceramic wafers, the conductive layer is formed by baking after applying the conductive paste, and at the same time, the separation into individual ceramic wafers can be automatically performed. , to simplify the work.

以下、添付の図面を参照して具体的にこの発明
を説明する。この例は凹部に導電層を形成する場
合について説明したものである。
Hereinafter, the present invention will be specifically described with reference to the accompanying drawings. This example describes a case where a conductive layer is formed in a recessed portion.

図において、1はセラミツクウエハ、2は電
極、3は凹部、4は導電部である。第1図に示す
セラミツク素子は、セラミツクウエハ1とその両
表面に表裏相対して形成された電極2と、表裏相
対する電極2を接続する導電部4とからなり、電
極2は相互に所定間隔をおいて平行に形成されて
いる。表裏相対する電極2は、第2図および第3
図に示すように、電極2が交差する端面1aに厚
さ方向に形成された凹部3内に形成された導電部
4により導通されている。なお、ウエハ1の表面
と凹部3の底面との交差部分は傾斜させてあり、
電極2と導電部4との接続が完全に行なわれるよ
うにしてある。
In the figure, 1 is a ceramic wafer, 2 is an electrode, 3 is a recess, and 4 is a conductive part. The ceramic element shown in FIG. 1 consists of a ceramic wafer 1, electrodes 2 formed on both surfaces thereof facing each other, and a conductive part 4 connecting the electrodes 2 facing each other, and the electrodes 2 are spaced apart from each other at a predetermined distance. They are formed parallel to each other. The front and back facing electrodes 2 are shown in FIGS. 2 and 3.
As shown in the figure, conduction is provided by a conductive portion 4 formed in a recess 3 formed in the thickness direction on the end surface 1a where the electrodes 2 intersect. Note that the intersection between the surface of the wafer 1 and the bottom surface of the recess 3 is inclined.
The electrode 2 and the conductive portion 4 are completely connected.

前記構造のセラミツク素子は、その表裏両表面
の電極が導通しているので、その片側の電極のみ
をボンデイングすればよく、従つてパツケージへ
のマウントおよびワイヤボンデイングをICチツ
プ等と同様に行うことができる。
Since the ceramic element with the above structure has conductive electrodes on both its front and back surfaces, it is only necessary to bond the electrode on one side, and therefore mounting to a package and wire bonding can be performed in the same way as an IC chip. can.

前記構造のセラミツク素子は、例えば、光シヤ
ツタを製造する場合、所定の厚さのPLZTその他
の透明な電気光学セラミツクウエハ1を、第4図
に示されるように、数枚以上重ねてワツクス等で
密着固定し、ブロツクにする。次いで、レーザビ
ーム、ダイヤモンドカツターその他の手段で、ウ
エハの端面に厚さ方向の凹部3を多数形成する
(第5図参照)。次いで、凹部3を形成した端面1
aの全面に銀ペーストを塗布し、これを焼付けて
導電層を形成する。空気中で銀ペーストを焼成し
焼付けると、ウエハを固着しているワツクスは燃
えて消失し、ウエハブロツクは個々のウエハに分
離する。各ウエハの表裏両表面に、アルミニウム
その他の適当な電極材料を真空蒸着、スパツタリ
ングなどの乾式メツキ法により電極層を形成した
後、フオトレジストをコーテイングして均一なレ
ジスト薄膜を積層形成する。このレジスト薄膜に
マスクを密着させて露光し、現像液で露光してい
ない部分のレジスト膜を溶解し、除去し、下層の
電極層を露出させ、これをエツチングした後、エ
ツチングマスクとして利用したレジストを除去
し、形成された電極を露出させる。次いで、ウエ
ハの端面を研磨し、その端面の突出部に形成され
た余分の導電層を取り去り、凹部内に形成された
導電層のみを残して導電部とすることにより電極
アレイを有するセラミツク素子が製造される。
For example, when manufacturing an optical shutter, the ceramic element having the above structure is obtained by stacking several or more PLZT or other transparent electro-optic ceramic wafers 1 of a predetermined thickness and coating them with wax or the like, as shown in FIG. Fix it tightly and make it into a block. Next, a large number of recesses 3 in the thickness direction are formed on the end surface of the wafer using a laser beam, a diamond cutter, or other means (see FIG. 5). Next, the end surface 1 with the recess 3 formed therein is
Silver paste is applied to the entire surface of a and baked to form a conductive layer. When the silver paste is fired and baked in air, the wax that holds the wafers together burns away and the wafer blocks are separated into individual wafers. Electrode layers are formed on both the front and back surfaces of each wafer by a dry plating method such as vacuum evaporation or sputtering with aluminum or other suitable electrode material, and then photoresist is coated to form a uniform resist thin film. This thin resist film is exposed with a mask in close contact with the resist film, and the unexposed parts of the resist film are dissolved and removed using a developer to expose the underlying electrode layer, which is then etched.The resist used as an etching mask is then etched. to expose the formed electrode. Next, the end face of the wafer is polished, and the extra conductive layer formed on the protruding part of the end face is removed, leaving only the conductive layer formed in the recessed part as a conductive part, thereby producing a ceramic element having an electrode array. Manufactured.

(実施例) 厚さ500μmのPLZT透光性セラミツクウエハを
100枚ワツクスで固め、その端面にダイヤモンド
カツターで500μmピツチで幅250μm、深さ100μm
の凹部を形成した後、その端面に銀ペーストを塗
布し、これを空気中800℃で焼成して導電膜を形
成した。この導電膜を形成した各ウエハを真空蒸
着装置に入れ、その両面にアルミニウムを蒸着し
た後、両面に合成ゴム糸のフオトレジスト(コダ
ツク社製KMR747)を塗布し、乾燥させて薄い
レジスト膜を形成し、これにフオトマスクを密着
させて紫外線を露光し、KMRデベロツパーで現
像後、KMRリンスで処理し、加熱してレジスト
を硬化させる。次いで、カセイソーダ系エツチヤ
ントを用いて露出したアルミニウムをエツチング
し、レジストを合成ゴム系レジスト用剥離剤(東
京応化工業製OMR502)で除去した後、ウエハ
を重ねてワツクスで固め、各ウエハの端面を研摩
し、洗浄して第1図〜第3図に示す光シヤツタを
得た。
(Example) A PLZT translucent ceramic wafer with a thickness of 500 μm
Harden 100 sheets with wax and cut the edges with a diamond cutter at 500μm pitch, width 250μm, depth 100μm.
After forming the concave portion, silver paste was applied to the end face, and this was baked in air at 800°C to form a conductive film. Each wafer with this conductive film formed thereon is placed in a vacuum evaporation device, and after aluminum is vapor-deposited on both sides, synthetic rubber thread photoresist (KMR747 manufactured by Kodatsu Corporation) is applied to both sides and dried to form a thin resist film. Then, a photomask is attached to this and exposed to ultraviolet light, developed with a KMR developer, processed with a KMR rinse, and heated to harden the resist. Next, the exposed aluminum was etched using a caustic soda-based etchant, and the resist was removed using a synthetic rubber-based resist remover (OMR502 manufactured by Tokyo Ohka Kogyo Co., Ltd.).The wafers were then stacked and solidified with wax, and the edges of each wafer were polished. After cleaning, the light shutters shown in FIGS. 1 to 3 were obtained.

この光シヤツタは、そのウエハ両表面に形成さ
れた相対する電極2が導電部で接続されているの
で、マウントおよびワイヤボンデイングを容易に
行うことができた。
In this optical shutter, since the opposing electrodes 2 formed on both surfaces of the wafer were connected by a conductive part, mounting and wire bonding could be easily performed.

なお、前記説明では角板形ウエハを用いたセラ
ミツク素子を例にしたが、これは円板形であつて
も同様であり、ウエハの両端面に凸部または凹部
を形成し、それに導電部を形成してもよい。また
セラミツク材料としてアルミナその他の任意の材
料を用いることができるのは言うまでもない。
In the above description, a ceramic element using a square plate-shaped wafer was used as an example, but the same applies to a disc-shaped wafer, in which protrusions or depressions are formed on both end faces of the wafer, and conductive parts are attached to them. may be formed. It goes without saying that alumina and other arbitrary materials can be used as the ceramic material.

(発明の効果) 以上の説明から明らかなように、本発明によれ
ば、セラミツク素子の表裏両面の相対する電極を
接続する導電層を形成するに際し、個々のセラミ
ツクウエハ毎に加工して導電層を形成する代わり
に、多数のセラミツクウエハをブロツクにしてい
るため、ワツクス等が緩衝剤として作用して破損
を防止すると共に凹部の形成から導電層の形成ま
での処理を簡使化でき、多数のセラミツクウエハ
への導電層の形成を一挙に行うことができる。ま
た、多数のセラミツクウエハを密着固定する手段
として使用するワツクス等の可燃性接合剤は、導
電性ペースト塗布後の焼成により燃焼して自然消
滅するため、個々のセラミツクウエハを分離する
特別な工程も不必要であり、従つて、導電層の形
成を容易にすると共に、セラミツク素子の量産化
を図ることができる。
(Effects of the Invention) As is clear from the above description, according to the present invention, when forming a conductive layer that connects opposing electrodes on both the front and back surfaces of a ceramic element, the conductive layer is processed for each individual ceramic wafer. Instead of forming a conductive layer, a large number of ceramic wafers are used as a block, so the wax etc. acts as a buffer to prevent damage, and the process from forming the recesses to forming the conductive layer can be simplified. A conductive layer can be formed on a ceramic wafer all at once. In addition, flammable bonding agents such as wax, which are used as means for closely fixing a large number of ceramic wafers, burn and disappear naturally when fired after applying the conductive paste, so a special process is required to separate the individual ceramic wafers. This is unnecessary, and therefore it is possible to facilitate the formation of a conductive layer and to mass-produce ceramic devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係るセラミツク素子の一例
を示す斜視図、第2図はその部分拡大図、第3図
は第1図の−線における断面要部拡大図、第
4図はセラミツク素子の製造過程における斜視
図、第5図はその部分拡大図である。 1……セラミツクウエハ、2……電極、3……
凹部、4……導電部。
Fig. 1 is a perspective view showing an example of a ceramic element according to the present invention, Fig. 2 is a partially enlarged view thereof, Fig. 3 is an enlarged view of a main part of a cross section taken along the - line in Fig. A perspective view of the manufacturing process, and FIG. 5 is a partially enlarged view thereof. 1... Ceramic wafer, 2... Electrode, 3...
Recessed portion, 4... conductive portion.

Claims (1)

【特許請求の範囲】 1 セラミツクウエハの両表面に相対して形成さ
れた複数の電極をその端面に形成された導電部を
介して接続してなるセラミツク素子を製造するに
当たり、セラミツクウエハの両表面に複数の電極
を形成する前または形成した後、 (イ) 複数枚のセラミツクウエハを積層して可燃性
接合剤で密着固定しブロツクとする工程と、 (ロ) 該ブロツクの端面にその積層方向に伸張する
多数の凹部を形成して各セラミツクウエハの端
面にその厚さ方向の凹部を多数形成する工程
と、 (ハ) 前記ブロツクの凹部を形成した端面に導電性
ペーストを塗布した後、これを焼成してセラミ
ツクウエハ端面に導電層を形成すると共に、
個々のセラミツクウエハに分離する工程と、 (ニ) 各セラミツクウエハの端面に形成された導電
層のうち前記凹部以外の端面に形成された導電
層を除去する工程と、 からなるセラミツク素子の製造方法。
[Scope of Claims] 1. In manufacturing a ceramic element in which a plurality of electrodes formed opposite to each other on both surfaces of a ceramic wafer are connected via conductive parts formed on the end faces thereof, both surfaces of the ceramic wafer are Before or after forming a plurality of electrodes on the wafer, (a) stacking a plurality of ceramic wafers and tightly fixing them with a flammable bonding agent to form a block; (c) forming a large number of recesses extending in the thickness direction on the end face of each ceramic wafer; is fired to form a conductive layer on the end surface of the ceramic wafer,
A method for manufacturing a ceramic device comprising the steps of: separating the ceramic wafers into individual ceramic wafers; and (d) removing the conductive layer formed on the end surface of each ceramic wafer other than the recessed portion. .
JP21411482A 1982-12-06 1982-12-06 Ceramic element and its manufacture Granted JPS59104623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21411482A JPS59104623A (en) 1982-12-06 1982-12-06 Ceramic element and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21411482A JPS59104623A (en) 1982-12-06 1982-12-06 Ceramic element and its manufacture

Publications (2)

Publication Number Publication Date
JPS59104623A JPS59104623A (en) 1984-06-16
JPH0416767B2 true JPH0416767B2 (en) 1992-03-25

Family

ID=16650458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21411482A Granted JPS59104623A (en) 1982-12-06 1982-12-06 Ceramic element and its manufacture

Country Status (1)

Country Link
JP (1) JPS59104623A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285219A (en) * 1985-10-03 1987-04-18 Fuji Photo Film Co Ltd Optical shutter array
JPH061305B2 (en) * 1985-10-03 1994-01-05 富士写真フイルム株式会社 Optical shutter array and manufacturing method thereof
JPS62218925A (en) * 1986-03-19 1987-09-26 Nec Corp Optical shutter array
JPS62231212A (en) * 1986-03-31 1987-10-09 Sumitomo Special Metals Co Ltd Production of optical shutter element
JPS62267719A (en) * 1986-05-15 1987-11-20 Nec Corp Optical shutter array

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112664A (en) * 1973-02-23 1974-10-26
JPS5225312B2 (en) * 1973-09-10 1977-07-06

Also Published As

Publication number Publication date
JPS59104623A (en) 1984-06-16

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