JPH0424735B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a data transmission device that transmits data between systems that mainly operate asynchronously. [Prior Art] Conventionally, a common method for transmitting data between asynchronous systems was to use FIFO (first-in, first-out) memory as a buffer between systems (interface
(See August 1984 issue, pages 268-270). for example,
When data is transmitted between the A system and the B system that operate asynchronously, the output of the A system 6a and the B system 6b are transmitted as shown in FIG.
The FIFO memory 7 is connected between the input of the A system 6a, thereby buffering the output of the A system 6a. Also, multiple asynchronous systems 6a to 6d
When transmitting data between the asynchronous systems, a configuration is adopted in which FIFO memories 7a to 7c are connected between the respective asynchronous systems, as shown in FIG. [Problems to be solved by the invention] However, in conventional data transmission devices, the FIFO memory only has a data buffering function, so if such a FIFO memory is used for data transmission between asynchronous systems, The problem is that multiple asynchronous systems can only be connected serially, and as a result, the entire system connected to FIFO memory can only be constructed as a pipeline processing mechanism using simple cascade connections, and its degree of freedom is extremely low. It was hot. This invention was made in order to solve the above-mentioned problems, and provides a data transmission device that can provide a large degree of freedom in system construction when constructing an entire system by connecting asynchronous systems. is intended to provide. [Means for Solving the Problems] The data transmission device according to the present invention uses self-propelled shift registers to configure input, output, branch, and merge data transmission paths, and at the branch section, the input data transmission path The branching control is performed by determining whether the data in the input data is data that should be branched and/or monitoring the availability of the branch data transmission path, and also monitors the availability of the input data transmission path at the merging section. The merging control is performed by [Operation] In addition to the data buffering function of the conventional FIFO memory, this invention has a data selective or load balancing branching function and a merging function, so that an asynchronous system etc. can be operated not only serially but also in parallel. can also be connected, giving greater flexibility in system construction. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a system of a data transmission device according to an embodiment of the present invention. In the figure, 5 is a data transmission path, 2a to 2c are branch parts, 3a to 3c are merging parts, and 1a to 1c are processing parts. Element 4 is an interface. In such a device, bucketed data flowing from an external system via the interface 4 reaches any of the processing elements 1a to 1c while circulating between the network elements 3a and 2a to 2c, and is processed by each of the processing elements 1a to 1c. After distributed processing is performed by the processing elements, the processing results are collected by the network elements 3b and 3c,
It is again sent to the external system via the interface 4. FIGS. 2 and 3 show the configurations of the branching section and merging section of the apparatus shown in FIG. 1 above. The branch section shown in FIG. 2 normally supplies data on the input data transmission line 10 to the output data transmission line 20 via the branch control section 40, and on the other hand, in the branch judgment section 50, the input data is sent to the main branch section. If it is determined that the data should be branched, and the free buffer monitoring section 75 confirms that there is a free buffer on the branch data transmission path 30, the input data is transferred to the branch data transmission path via the branch control section 40. 30 branches. Further, the merging section shown in FIG. 10,2
If it is confirmed that there is an empty buffer in 0, the merging control unit 60 controls the merging data transmission line 7
0 data is merged into the output data transmission path 20. Here, FIG. 4 shows the configuration of the asynchronous self-running shift register that constitutes each of the data transmission paths. This asynchronous self-running shift register is a register in which input data is automatically shifted in the output direction without using a shift clock, provided that the next register is empty. It has a buffer function. As shown in the figure, each stage of this asynchronous self-running shift register is composed of a parallel data latch and a transfer control circuit C (hereinafter referred to as a C element) which provides a rising edge trigger to the parallel data latch. Further, this C element is composed of, for example, a 3-input NAND circuit C11 and 2-input NAND circuits C12 and C13, as shown in FIG. The above C element receives two inputs, P0 and P3,
It outputs two outputs, P1 and P2, and the internal state of the C element is determined by the states of these four signals, and takes nine states, S0 to S8, as shown in Table 1 below. In the following explanation, the theoretical values "0" and "1" refer to the low level and signal value, respectively.
Equivalent to high level.

〔Effect of the invention〕

As described above, according to the data transmission device of the present invention, the input, output, branch, and merge data transmission circuits are configured using self-running registers, and in the branch section, the branch data transmission line is connected to the input, output, branch, and merge data transmission circuits. Input data branching control is performed according to the result of monitoring the idle state and/or the result of determining whether the input data on the input data transmission path is data that should be branched, and at the merging section, the input data transmission path is Since the merging control is performed according to the monitoring results of the vacant status,
Using such a data transmission device, it is possible to realize a network with an extremely high degree of freedom.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of its branching section, and FIG. 3 is a schematic block diagram of its merging section.
FIG. 4 is a schematic block diagram showing an example of the configuration of an asynchronous free-running shift register constituting the transmission line of the data transmission device, FIG. 5 is a diagram showing an example of a specific circuit configuration of the C element, and FIG. The figure shows the state transition of the C element, FIG. 7 shows a specific circuit configuration example of the branch section shown in FIG. 2, and FIG. 8 shows the specific circuit configuration of the confluence section shown in FIG. 3. FIG. 9 is a diagram showing an example of the configuration of a data jam detection circuit, and FIGS. 10 and 11 are block diagrams showing the configuration of a conventional asynchronous system. 10...Input data transmission path, 11, 21, 3
1, 61a to 61c, 71...Parallel data latch, 12, 22, 32, 62a to 62c, 72...
...C element, 20... Output data transmission line, 30...
Branch data transmission line, 40... Branch control unit, 50...
...branch determination section, 60...merging control section, 70...merging data transmission path, 75, 80...vacant buffer monitoring section. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. Constructed using a shift register consisting of a plurality of data storage means and a transfer control circuit in each stage that controls the data storage means in its own stage according to control signals from transfer control circuits in adjacent stages. an input data transmission path, an output data transmission path, a branch data transmission path, and a merged data transmission path, and an empty buffer monitoring means for monitoring the empty state of the branch data transmission path, or input data on the input data transmission path. data branching means having at least one branching judgment means for judging whether or not the input data is data to be branched, and controlling branching of the input data according to at least one of the monitoring result or the branching judgment result; Data transmission characterized by comprising: a vacant buffer monitoring means for monitoring the vacant state of the data transmission path, and a data merging means for controlling the merging of data on the merging data transmission path according to the monitoring result. Device.