JPH0424743B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a data transmission circuit comprising an asynchronous self-propelled shift register, and particularly to means for detecting whether data is flowing through the shift register. [Prior Art] In general, an asynchronous self-running shift register can push in and pop out data independently and simultaneously, and furthermore, the pushed in data can be pushed in and out on the condition that the next stage shift register is empty. For example, as shown in FIG. 7, transfer control signals from parallel data buffers (data storage means) 110 to 114 and transfer control circuits in adjacent stages are used. It is composed of a transfer control circuit for each stage that controls the parallel data buffer of its own stage according to the timing, and this transfer control circuit includes a coincidence element (hereinafter referred to as C element).
Theoretical circuits 120 to 124 called
The C (coincidence) output is used as a transfer control pulse. In this example, the asynchronous self-propelled shift register 1
The 00 data is in the form of a packet consisting of multiple words, and each word is separated from the data part.
BOP (Beginning of Packet), EOP (End of Packet)
It is assumed that the BOP of the first word is 1, the EOP of the last word is 1, and both BOP and EOP are 0 in other cases. In addition, as shown in the theoretical value table below, the C element outputs a C output at the same level as the input level when the two inputs X and Y match, and otherwise holds the previous output level (HOLD). It is something to do. Such an asynchronous self-running shift register has a data buffer function and can be used to connect asynchronous systems.

[Problem that the invention seeks to solve]

In data transmission circuits configured using such asynchronous free-running shift registers, it has conventionally been possible to detect whether data is occupied or not occupied only in a particular stage; When a transmission circuit branches or merges a packet consisting of multiple words into another data transmission circuit, simply detecting the occupancy of data in one stage is not sufficient to perform such branching or merging smoothly and quickly. . This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and is a data transmission method that can detect data blockage, that is, data stagnation (stationary state) in an asynchronous self-propelled shift register. The purpose is to provide circuits. [Means for Solving the Problems] A data transmission circuit according to the present invention is provided with a blockage detection means for detecting data retention in an asynchronous self-propelled shift register. [Operation] In the present invention, since the clogging detection means detects the occupied state of the invented data over a predetermined number of stages of the asynchronous self-propelled shift register, it becomes clear whether or not data is retained. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a data transmission circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 7 indicate the same parts. 200 is a blockage detection circuit that detects data retention (stationary state) occurring in three stages of the asynchronous self-propelled shift register 100; The outputs of open collector type non-inverting buffer drivers 210 to 212 to which transfer control signals are input are wired-OR connected. Note that 220 is a pull-up resistor. Next, the operation will be explained. When the C element's C output is 1, it indicates that data is occupied in the parallel data buffer of the relevant stage, and if at least one C output is 0, data is shifted from the previous stage of the relevant stage. , data blockage (stagnation) does not occur. However, all parallel data buffers 110 to 1
12 is occupied by data, and if a data blockage occurs, all C elements 120 to 122
The C output of becomes 1, and the non-inverting buffer driver 2
Since all of the outputs from 10 to 212 are 1, the detection signal BRPACK of the main blockage detection circuit 200 is 1, indicating that data is stagnant across the three stages. This embodiment configured as described above has, for example, the fourth
It can be used in a data-driven processor as shown in the figure to increase the speed of its arithmetic processing. That is, in FIG. 4, data packets flowing from an external system via the interface 400 are distributed between the processing elements 407 to 409 while circulating between the network elements 403 to 406, and then transferred to the network element 401. and 402, the processing results are collected and sent to the external system again via the interface 400, but by configuring the branching and merging parts as shown in FIGS. 5 and 6, Branching and merging can be performed smoothly, and as a result, the throughput of a data-driven processor can be improved. That is, according to the branching section shown in FIG. 5, the buffer clogging monitoring section 404e constantly monitors the data accumulation on the branch data transmission line 404c, and when the data accumulation is resolved, it notifies the branching control section 404d of this fact. The branch control unit 404d normally provides the data input to the input data transmission path 404a to the output data transmission path 404b;
When the buffer clogging monitoring unit 401e detects that the data clogging has been resolved, the data on the input data transmission path 404a is transferred to the branch data transmission path 40.
4c. In this way, as soon as it is determined that the data blockage in the branch data transmission line has been cleared, the data is branched, so that data branching is performed smoothly and at high speed, and the data can be branched to processing elements that have free space. This makes it possible to easily distribute the load on data-driven processors. Note that the input data transmission path 404a, the output data transmission path 404b, and the branch data transmission path 404c are the seventh
The buffer clogging monitoring section 404e is composed of the asynchronous self-propelled shift register shown in the figure, and is configured as shown in FIG. Further, 404f is an input data arrival monitoring unit. In the above description of the branch section, the branch data transmission line 404c is monitored by the buffer clogging monitoring section 404e, and the branch is made when there is no data retention. By adding conditions for selective branching depending on input data, a more sophisticated branching section can be constructed. Further, according to the merging section in FIG. 6, the merging control section 40
1e normally provides data output from the input data transmission path 401a to the output data transmission path 401b, and when the merging data arrival monitoring section 401f detects that data has arrived at the merging data transmission path 401c, the merging control section 401e It controls so that the data on the merged data transmission path 401c is provided to the output data transmission path 401b. However, when the buffer clogging monitoring unit 401d detects data retention on the input data transmission path 401a and the output data transmission path 401b, such merging is not performed. In this way, when data is flowing through the input data transmission path and the output data transmission path, the data is immediately merged, so that the data can be merged smoothly and at high speed in the data-driven processor. The input data transmission path 401a, the output data transmission path 401b, and the combined data transmission path 401c are composed of the asynchronous self-propelled shift register shown in FIG. 7, and the buffer clogging monitoring section 401d is configured as shown in FIG. In the above embodiment, one C element per stage of the parallel data buffer was explained.
As shown in FIG. 2, a configuration may be adopted in which each stage of the parallel data buffer has two C elements, and the same effect as in the above embodiment can be obtained. In FIG. 2, 140 to 151 are open collector type inverters, 130 to 136 are C elements, and 160 is a 2-input NOR gate.
C output of 0,132,134 becomes 1,131,1
33, 135 becomes 0, or when the C output of C elements 131, 133, 135 becomes 1, 1.
When the C outputs of 30, 132, and 134 are 0, the blockage detection signal BRPACK becomes 1. However, it is preferable to use the C element in Fig. 3 b for the C element in Fig. 1, and it is desirable to use the C element in Fig. 3 a for the C element in Fig. 2, but it is preferable to use the C element in Fig. 3 c. It may be configured as follows. In this figure 3, 30
0,320 to 322 are 2-input NAND gates,
301 and 302 are 2-input NOR gates, 323
is a negative logic three-input NOR gate, and 324 is an inverter. Furthermore, although the above embodiment describes a case in which data is transmitted between asynchronous systems, the present invention can be similarly applied to a case in which data is transmitted between synchronous systems, and in this case, the C element is used as a synchronous control circuit. Bye. [Effects of the Invention] As described above, according to the data transmission circuit according to the present invention, data retention is detected by detecting occupancy or non-occupancy of each stage of the asynchronous shift register. This has the effect that it is possible to very easily detect data blockage in the asynchronous shift register, which could not be detected.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a data transmission circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing another embodiment of the present invention, and FIG. 3 is a circuit example of the C element in FIGS. 1 and 2. FIG. 4 is a diagram showing the configuration of a data-driven processor, FIGS. 5 and 6 are diagrams showing the configuration of the branching part and merging part in FIG. 4, and FIG. 7 is a diagram showing the configuration of a conventional data transmission path. FIG. In the figure, 100 is an asynchronous self-running shift register, 110 to 112 are parallel data buffers (data storage means), 120 to 122, 130 to 13
6 is a C element (transfer control means), 200 is a clogging detection circuit, 210 to 212 are open collector type non-inverting buffer drivers, 140 to 141 are open collector type inverters, 160 is a two-input NOR gate, 220 to 222 is a pull-up resistor.

Claims (1)

[Scope of Claims] 1. A shift register comprising a plurality of data storage means and transfer control means of each stage that controls the data storage means of its own stage in response to a control signal from the transfer control means of an adjacent stage. In the data transmission circuit, the transfer control means includes a matching element consisting of two MOS transistors of opposite conductivity type connected in series between the power supply and the ground, and a CMOS inverter connected to the output of the MOS transistor. The data storage means is constructed by connecting the outputs of open collector type non-inverting inverters provided in respective required stages of the shift register and into which the control signal from the matching element is inputted, by wire-OR connection. 1. A data transmission circuit comprising blockage detection means for detecting a stationary state of data or data packets generated over one or more predetermined stages.