JPH0431189B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is an integrated injection system (I ² L) that does not require much withstand voltage and operates at high speed with low power consumption.
Logic) and a normal bipolar transistor that requires high breakdown voltage.

I ² L is a vertical transistor with an inverted structure in which the collector region, which is the signal output end region, is provided on the surface of the semiconductor substrate, and is complementary to this in which the collector region and base region are shared with the base region and emitter region of the above vertical transistor, respectively. It consists of a type of lateral transistor. I ² L is attracting attention as a logic element that allows high density operation because it does not require isolation between elements, and operates with low power consumption.

I ² L also has the advantage that it can be easily integrated on the same semiconductor substrate with ordinary bipolar transistors.

By the way, when I ² L and a normal bipolar transistor are integrated on the same substrate in the same manufacturing process, the current amplification factor of the reverse structure vertical transistor in the I ² L part must be increased to maintain the high speed of I ² L. If this happens, the breakdown voltage of the bipolar transistor becomes extremely low, and conversely, if the breakdown voltage of the bipolar transistor is increased, there is a problem in that the high-speed performance of I ² L will be impaired. Several methods have been proposed to solve this problem, but at present none are sufficient.

The present invention has been made in view of the above-mentioned points, and provides a method for manufacturing a semiconductor device in which I ² L and a normal bipolar transistor can be integrated without impairing their respective characteristics.

That is, the present invention provides a semiconductor device that integrates an I ² L having a first vertical transistor with an inverse structure and a second vertical transistor that is a normal bipolar transistor. At least a region immediately below the collector region is formed deeply as a low concentration layer, a portion surrounding the collector region and a base region of the second vertical transistor are formed with a relatively shallow concentration, and The collector region and the emitter region of the second vertical transistor are formed at the same time, which simplifies the manufacturing process and enables high-speed operation and high breakdown voltage.

Embodiments of the present invention will be described below with reference to the drawings. Figures 1a to 1e show the manufacturing process of one embodiment, in which an I ² L having an inversely structured npn vertical transistor (first vertical transistor) and pnp lateral transistor is used as a logic element.
This is also an example in which a normal npn bipolar transistor is integrated as the second vertical transistor. To explain this according to the manufacturing process, p ^- −Si
After forming the n ⁺ layers 2 ₁ and 2 ₂ by diffusion in the I ² L portion and the bipolar transistor portion of the substrate 1, the n layer is epitaxially grown on the entire surface. Next, the entire surface of this substrate is oxidized, a predetermined enlarged window is opened, and a p ⁺ layer 4 for element isolation, an n ⁺ layer 5 that becomes the grounding end of the I ² L section, and a layer for extracting the collector of the bipolar transistor section are removed.
An n ⁺ layer 6 is formed by diffusion, and ions are implanted into the active base region directly under the collector region of the I ² L portion ^.
Form layers 7 ₁ and 7 ₂ in advance.b. Next, by applying a high-temperature thermal process for a predetermined time, the p ⁺ layer 4 becomes p ^- -Si
In order to reach the substrate 1, the n ⁺ layers 5 and 6 are respectively
n ⁺ layers 2 ₁ , 2 ₂ and p ^- layers 7 ₁ , 7 ₂
is sheet resistance 3000~5000Ω/□, diffusion depth 3~
Make it a low concentration layer of about 3.5μmc. At this time, the n ⁺ layers 2 ₁ and 2 ₂ also float up into the n layer 3 so that the p ⁻ layers 7 ₁ and 7 ₂ are in contact with the n ⁺ layer 2 ₁ . continue,
The p layer 8 which becomes the emitter region of the Pnp lateral transistor for the injector in the I ₂ L part, the collector region of the lateral transistor, that is, the reverse structure for the inverter
A p-layer 9 serving as a base region surrounding the collector region of the npn vertical transistor and a p-layer 10 serving as the base region of the bipolar transistor.
For example, by using boron ion implantation and diffusion, a relatively high concentration is simultaneously formed so that the sheet resistance is 80 to 180 Ω/□ and the diffusion depth is about 2 μm. after that,
The n ⁺ layer 11 ₁ , 1 serves as the output end region of the I ² L section, that is, the collector region of the inverted vertical transistor.
1 ₂ and becomes the emitter region of the bipolar transistor. Depth 1.3 ~ by simultaneous diffusion of n ⁺ layer 12
Formed to a thickness of approximately 2.0 μm, and finally by vapor deposition and patterning of Al, the signal input end electrode IN, signal output end electrode OUT ₁ , OUT ₂ , ^ground electrode GND, external power application electrode +V _EE and bipolar transistor of the I 2 L section are formed. form an emitter electrode E, a base electrode B, and a collector electrode C, respectively. Note that the n ⁺ layer 11 ₁ , 1
1 ₂ and n ⁺ layer 12 at the same time,
The diffusion depth differs depending on the concentration of each base region. For example, when the former is about 1.7 μm, the latter is about 1.7 μm.
It becomes 1.4μm.

In the device obtained in this way, the inverted structure npn vertical transistor for the inverter in the I ² L part has a low concentration layer in the active base region directly under the collector, so that even if the base width is 1 to 2 μm, there is no current. The amplification factor is sufficiently large, and the low concentration layer in the active base region is made deep so as to be in contact with the n ⁺ layer 2 ₁ , and a relatively high concentration external base region is provided surrounding the active base region. High-speed operation is possible, and a large fanout can be achieved with one I ² L gate. Also, looking at the bipolar transistor section,
Since the base region of this npn vertical transistor leaves the n layer 3 of 1 to 1.5 μm up to the n ⁺ layer 2 ₂ , a high breakdown voltage between the collector and the emitter is ensured. Furthermore, due to the difference in base concentration between the I ² L section and the bipolar transistor section, the emitter region diffusion of the bipolar transistor section is shallower than the collector region diffusion of the I ² L section. This means that it can be made shallow, which is advantageous in further increasing the withstand voltage of the bipolar transistor.

FIG. 2 shows another embodiment of the invention, corresponding to FIG. 1e. Portions corresponding to those in FIG. 1e are designated by the same reference numerals and detailed explanations will be omitted.
In this example, p ⁻ is the low concentration base region of the I ² L part.
The layer 7' is diffused not only directly under the collector but also over the entire base region, with its diffusion end in contact with the n ⁺ layer ₂₁ , and the layer 7' is formed again in the collector region from above the p ^- layer 7' at a relatively high concentration. The p layer 9 surrounding the p layer 10 serves as the base region of the bipolar transistor section.
At the same time, it is formed by diffusion to be shallower than the p ^- layer 7'. In this example, compared to the previous example,
There ^is an n
Since layer 3 is not left behind, carrier accumulation in the emitter region of the I ² L portion is reduced, and I ² L can be operated at higher speed.

As explained in detail above, according to the present invention, various types of logic elements I ² L capable of high-speed operation and sufficient fan-out and bipolar transistors requiring high breakdown voltage are integrated without impairing their respective characteristics. A method for manufacturing a semiconductor device useful for logic circuit configuration can be provided.

[Brief explanation of drawings]

1A to 1E are diagrams showing the manufacturing process of one embodiment of the present invention, and FIG. 2 is a diagram showing another embodiment corresponding to FIG. 1E. 1... p ^- -Si group, 2 ₁ , 2 ₂ ... n ⁺ layer, 3... n layer, 4...
p ⁺ layer (for element isolation), 5...n ⁺ layer (for grounding), 6...
n ⁺ layer (for collector extraction), 7 ₁ , 7 ₂ , 7'... p ^- layer (low concentration base region), 8... p layer (injector emitter region), 9... p layer (high concentration base region),
10...(high concentration base region), 11 ₁ , 11 ₂ ...n ⁺
layer (collector region), 12...n ⁺ layer (emitter region).

Claims (1)

[Claims] 1. A first vertical transistor having an inverse structure in which a collector region serving as a signal output end region is provided on the surface of a semiconductor substrate, and a first vertical transistor having a collector and a base region respectively shared with the base and emitter regions of the first vertical transistor When manufacturing a semiconductor device in which a logic element consisting of a vertical transistor and a complementary transistor is integrated on the same semiconductor substrate together with a second vertical transistor whose emitter region is provided on the surface of the semiconductor substrate, forming a semiconductor substrate by providing a low concentration layer of a second conductivity type thereon via a buried layer of a second conductivity type which becomes the emitter of the first vertical transistor and the collector of the second vertical transistor, respectively; forming a low concentration layer of a first conductivity type deeply in at least a collector region position of the first vertical transistor to form an active base region reaching the buried layer; and a high concentration layer of a first conductivity type. forming an external base region surrounding the collector region of the first vertical transistor and a base region of the second vertical transistor; A method for manufacturing a semiconductor device, comprising the step of simultaneously forming a collector region of the second vertical transistor and an emitter region of the second conductivity type of the second vertical transistor.