JPH0442758B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

Traditional RAM (Random Access Memory)
When reading or writing data, a read-only memory (ROM) or ROM (read-only memory) reads or writes data one bit at a time or for each group of data of a predetermined number of bits, such as one byte (8 bits), by supplying an address signal from the outside. , reading, and writing.

Therefore, when reading a set of arbitrary multi-bit data, such as reading data for a display, conventional RAM or
In the case of ROM, an address signal is generated in the CPU, etc. for each bit or byte, and the RAM
Since the data must be supplied to the address signal or ROM for random access, the operation of the external device that supplies the address signal becomes complicated, and the read speed cannot be increased.

An object of the present invention is to provide a semiconductor memory device having a random access function and a serial access function.

Another object of the present invention is to provide a semiconductor memory device that can perform read and write operations at high speed during serial access operations.

Further objects of the invention will become apparent from the following description and drawings.

According to embodiments of the present invention, which will be described later, a semiconductor memory device is provided with an internal address generation circuit that can be initialized, and an internal address signal that is continuously changed is generated from the internal address generation circuit. In addition to the random access function, the device is also provided with a serial access function. This makes it possible to continuously read and write data of any number of bits without receiving address signals from the outside, reducing the burden on external devices such as the CPU, and improving ease of use.

Furthermore, according to the embodiments of the invention described later,
In order to perform high-speed read and write operations when executing the newly added serial access, the output of the sense amplifier is supplied to the register via switch means.

The present invention will be explained below based on the drawings.

As an example, a case where the present invention is applied to a 64K bit dynamic RAM will be explained.

In FIG. 1, each block surrounded by dotted lines is formed on one semiconductor substrate using well-known semiconductor integrated circuit technology.

In the circuit of the embodiment shown in FIG. 1, an address signal is supplied twice from a predetermined address pin using an address multiplex method, and data is read and written bit by bit through random access. By supplying an appropriate control signal from the vacant No. 1 pin of the 16-pin package, multiple bits of data can be read and written sequentially.

In FIG. 1, reference numeral 1 denotes a memory cell array in which 64K bit memory cells are arranged in a matrix of, for example, 256 x 256 bits.

2a and 2b are address buffer circuits, and these address buffer circuits 2a and 2b include
X-system address signals A _x0 -A _x7 and Y-system address signals A _y0 -A _y7 which are given twice from a CPU (microprocessor) or the like are input.

3a, 3b are the address buffer circuits 2a,
2b, address signals A _xi , _xi , a _yi , _yi are received from the memory cell array ₁ .
These are an X decoder and a Y decoder for selecting one memory cell corresponding to A _yi .

4 is an internal signal generation circuit, and this internal signal generation circuit receives a row address strobe signal (hereinafter referred to as a signal) and a column address strobe signal (hereinafter referred to as a signal) supplied from the CPU, etc.
Based on the address buffer circuits 2a, 2
Control signals φ _x1 , φ _x2 , φ _y1 , φ _y2 that operate the b,
occurs.

The internal signal generation circuit 4 generates internal control signals φ _c , based on the external control signal φ supplied from pin 1.
φ _s also occurs.

5a and 5b are counter circuits, and the counter circuit 5a is supplied with a clock from the internal signal generating circuit 4 and counts up. When the counter circuit 5a overflows, a carry is sent to the counter circuit 5b, and the counter circuit 5b is counted up by this carry. Counter circuits 5a and 5b each consist of a binary counter having a number of digits equal to the number of pits of row address signal _Axi and column address signal _Ayi , and the output thereof is used as an internal address signal.

6a and 6b are external address signals which are generated by the control signal _φs supplied from the internal signal generating circuit 4.
This is a switch circuit for selectively supplying internal address signals from A _xi , A _yi or the counter circuits 5a, 5b to the address buffer circuits 2a, 2b. Note that 7 is a data input/output buffer circuit.

In the above circuit, when the external control signal φ supplied from the 1st pin is at a high level, data is read and written bit by bit by normal random access.

That is, when the external control signal φ is at a high level, the internal control signal φ _s is kept at a high level, and the switch circuits 6a and 6b are switched between the counters 5a and 5.
Cut the output of external address signal A _xi , A _yi
is supplied to the address buffer circuits 2a and 2b. Then, when the signal is changed from high level to low level, control signal φ _x1 is changed to high level, and address buffer circuit 2a takes in address signals A _x0 to A _x7 through switch circuit 6a and internalizes them. Latch.
As a result, signals a _xi and _xi are formed and supplied to the X decoder 3a. The X decoder 3a is
When the control signal φ _x2 formed based on the RAS signal rises to a high level a little later than the signal φ _x1 , only one word line corresponding to the address signal A _xi is brought to the selection level.

Next, when the signal is changed from high level to low level, control signal φ _y1 supplied from internal signal generation circuit 4 to address buffer circuit 2b is changed to high level. Then, at this time
Column address signals A _y0 to A _y7 supplied from the CPU, etc.
is taken into the address buffer circuit 2b and latched. Subsequently, when the control signal φ _y2 is changed to high level, the Y decoder 3b selects one data line corresponding to the address signal A _yi by the output signals a _yi and _yi of the address buffer circuit 2b. do.

As a result, one bit of data corresponding to the external address signals A _xi and A _yi is read from the memory cell array 1 and output from the input/output buffer circuit 7, or one bit of data input to the input/output buffer circuit 7 is read out from the memory cell array 1 and output from the input/output buffer circuit 7. data is written to the selected memory cell.

Switching between reading and writing data is performed by changing the state of the input/output buffer circuit 7 by a write enable signal supplied from the CPU (not shown).

Next, the serial access operation in the circuit shown in FIG. 1 will be explained.

When the external control signal φ supplied from pin 1 changes from high level to low level as shown in FIG. 2, the counters 5a and 5b are reset by the signal output from the internal signal generating circuit 4. Ru. Further, the internal control signal φ _s supplied to the switch circuits 6a and 6b is changed from high level to low level. As a result, the switch circuits 6a, 6
b cuts off the external address signal and outputs the counter 5.
The state is such that the outputs (internal address signals) of a and 5b are supplied to address buffer circuits 2a and 2b.

Also, after the external control signal φ changes to low level, the signal is supplied from the outside in synchronization with the control signal φ _c supplied from the internal signal generation circuit 4 to the counter 5a at the timing when the signal changes from high level to low level. The address signal A _xi is taken into the counter 5a. Subsequently, the address signal yi is taken into the counter 5b at the timing when the signal changes to low level.

Thereafter, when the external control signal φ supplied from pin 1 is changed at an appropriate period as shown in FIG. 2, a clock C having the same period is supplied from the internal signal generation circuit 4 to the counter 5a. Then, the counter 5a counts up.

The outputs of the counters 5a and 5b, which are increased in this way, are sent to the address buffer circuits 2a and 2b.
When the data is supplied to the address, the addresses are updated one by one by the decoders 3a and 3b, and data is continuously read and written.

Therefore, as shown in FIG. 4B, when you want to continuously read data of an arbitrary number of bits stored from a desired address (first address) to a desired address (last address) in the memory cell array, After the control signal φ is set to low level,
The first address may be input into the counters 5a, 5b in synchronization with the fall of the RAS signal, and a clock corresponding to the number of bits of the data to be read may be applied to the external control signal φ and supplied from the No. 1 pin.

The number of bits of data to be read is, for example,
It can be obtained by subtracting the first address from the last address using the ALU (Arithmetic Logic Unit) in the CPU.

However, instead of forming a predetermined number of clocks with an external device such as a CPU, two counters and an ALU are provided inside the RAM, and the difference (number of data bits) between the first address and the last address is calculated using this ALU. The second counter is inputted into a second counter, the second counter is down-counted by a clock supplied from the outside, and when the second counter reaches 0, the counter 5a stops counting up, so that the desired address can be moved from the desired address to the desired address. Data of an arbitrary number of bits may be read out.

In addition, the first address is set in the counters 5a and 5b, and a register for setting the final address and a comparison circuit for comparing this register with the values of the counters 5a and 5b are provided. When the values of the counters 5a and 5b match, the count-up of the counters 5a and 5b is stopped,
Data may be read from a desired address area.

In the above case, as shown in FIG. 3, the row address signal of the first address is signaled at the first falling edge after the external control signal φ is set to low level.
A _xi and the column address signal A _yi are taken into counters 5a and 5b at the first falling edge of the signal,
Next, the row address signal A _xi of the final address may be taken into the register at the second falling edge of the signal, and the column address signal A _yi at the second falling edge of the signal may be taken into the register.

If the above circuit is intended for use in which all data from address 0 to the last address is continuously read out as shown in Figure 4A, for example, a reset signal is generated when the power is turned on. A circuit is provided so that the counters 5a and 5b are reset at the same time as the power is turned on. Then, in the same way as above, by supplying a clock generated based on the external control signal φ to the counter 5a and causing it to count up, all addresses can be accessed and all data can be read out sequentially and continuously. can.

In addition, in the case of serial access operation, the above-mentioned control signals φ _x1 , φ _x2 , φ _y1 , φ _y2 and read operation,
Various internal control signals necessary for the write operation, such as internal control signals for operating the sense amplifier, are formed based on the external control signal φ. That is, in this case, the internal signal generating circuit 4 generates the various control signals described above every time the external control signal φ changes (for example, from a high level to a low level).

In the above embodiment, the data is read out sequentially from the first address to the last address, but it is also possible to read the data in the reverse direction by inputting the last address into the counters 5a and 5b and counting down. is also possible.

In addition, in the above embodiment, 64K bits is used as an example.
Although the case where it is applied to RAM has been explained, the present invention is 256K
It can also be applied to bit RAM, ROM, etc.

For 256K bit RAM, pin 1 is used as address _A8 in the case of a 16-pin package, so
There is no longer a pin for supplying the external control signal φ in the above embodiment. However, in this case,
Random access mode or serial access mode is determined based on the difference in timing between the RAS signal and the signal change, and at the time of serial access, a clock is formed that causes the counter 5a to count up based on the signal or periodic changes in the signal. Supplied to the counter 5a,
An internal address that changes continuously can be generated by the counters 5a and 5b. Further, the above-mentioned various control signals necessary for the read operation and the write operation are generated by the internal signal generation circuit 4 based on the signals or changes in the signals.

Next, another embodiment of the present invention will be described using FIG. 5.

In this embodiment, a buffer register 9 is provided at the next stage of the sense amplifier 8 to speed up the read operation.

A switch circuit 10 is provided between the sense amplifier 8 and the buffer register 9 to connect or disconnect the circuits under the control of the control signal _φSB output from the internal signal generating circuit 4. ing. That is, the switch circuit 10 is
By the control signal _φSB from the internal signal generation circuit 4,
The output of the sense amplifier 8 is either transmitted to the buffer register 9 or not transmitted.

Further, in this embodiment, switch circuits 6a and 6b for switching between external addresses and internal addresses are provided downstream of address buffer circuits 2a and 2b. The switch circuits 6a and 6b selectively transfer the output signals of the address buffer circuits 2a and 2b or the outputs of the counters 5a and 5b to the X decoder 3a and the Y decoder according to the control signal φ _S output from the internal signal generation circuit 4. 3b. The counter 5a is incremented by the carry CR from the counter 5b.

In the circuit of the embodiment shown in FIG. 5, data in the memory cell array 1 can be continuously read from a desired row to a desired row in the serial access mode, as shown in FIG. 4C.

In the random access mode, an external address signal supplied from the outside to the address buffer 2a
The X decoder 3a sets the corresponding word line to the selection level in accordance with _Axi . Then, the data of all memory cells connected to that word line are simultaneously read out to the sense amplifier 8 and held. Then, according to the external address signal _Ayi supplied to the address buffer 2b, the Y decoder 3b
One of the data is selected and outputted via the Y decoder 3b and the input/output buffer 7.

Therefore, in the serial access mode, the control signal φ _C from the internal signal generation circuit 4 allows
An address signal A _xi indicating the start address supplied from the CPU or the like is taken into the counter 5a. Then, the switch circuit 6a is controlled by the internal control signal _φS.
is switched, the output signal of the address buffer 2a is cut off, and the output of the counter 5a is supplied to the X decoder 3a. As a result, one row of data including the start address is read out to the sense amplifier 8. All bits of the read data for one row are transferred to the buffer register 9 at the same time. on the other hand,
The counter 5b is counted up by the clock C supplied from the internal signal generating circuit 4.
Upon receiving the output of this counter 5b, the Y decoder 3b
causes the data held in the buffer register 9 to be output one bit at a time. When the data in the buffer register 9 is being read out sequentially by the Y decoder 3b, the buffer register 9 and the sense amplifier 8 are separated by the switch circuit 10, and the sense amplifier 8 is connected to the memory cell array 1. The next row of data is read out and held.

As a result, there is no apparent delay in the read operation due to a delay in the rise of the word line to the selection level, making it possible to perform a high-speed read operation.

The data of the first row to be read and subsequent rows can be read, for example, after the data of the previous row has been transferred to the buffer register 9 and the counter 5b has started counting up, but before the counter 5b completely overflows. , counter 5b to counter 5
It is sufficient if the carry is sent to a and the counter 5a is incremented by one. As a result, the word line of the next row is driven and the data is read to the sense amplifier 8 before the reading from the buffer register 9 is completed.

In the case of serial access operation, the control signal φ _x2 is, for example, synchronized with the carry signal CR.
The control signal φ _y2 is generated by the internal signal generating circuit 4 based on the control signal φ, for example. Furthermore, when this mode is set, various control signals necessary for read and write operations are generated by the internal signal generation circuit 4 based on, for example, a signal synchronized with the carry signal CR, an external control signal φ, etc.

As explained above, the semiconductor memory device according to the present invention has a serial access function in addition to a random access function.
When a group of data is to be read out continuously, by using the serial access mode, an internal address signal is generated and desired data is automatically read out. Therefore, there is no need to form an address signal bit by bit in order to read data in an external device.
This reduces the burden on external devices such as the CPU and improves the usability of the storage device.

Furthermore, a buffer register is provided after the sense amplifier that reads and latches one row of memory cell data at a time, and while the data transferred from the sense amplifier to this buffer register and held is being read, the next A high-speed read operation is made possible by reading out and latching the data in the row to the sense amplifier. Furthermore, since a word line only needs to be selected once to write data for one row, high-speed write operations are possible.

The invention is not limited to the above embodiments. Although the above embodiment is a semiconductor memory device using an address multiplex method, for example, a semiconductor memory device of a method in which an X-system external address signal A _xi and a Y-system external address signal A _yi are supplied simultaneously may be used. It may also be a storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a timing chart of control signals in the serial access mode, and FIG. 3 is a timing chart of a control signal in the serial access mode in another configuration column. FIG. 4 is a memory map showing the data read/write method in the serial access mode in each embodiment, and FIG. 5 is a block diagram showing another embodiment of the present invention. 1...Memory cell array, 3a, 3b...Decoder, 4...Internal signal generation circuit, 5a, 5b...
Internal address generation circuit (counter).

Claims (1)

[Claims] 1. A memory array in which a plurality of memory cells are arranged in a matrix, a decoder circuit to which an address signal is input and selects one bit from within the memory array, and an internal address signal. an internal address generation circuit, a sense amplifier, a buffer register, and a circuit provided between the sense amplifier and the buffer register to transmit or not transmit the sense amplifier output to the buffer register; a first switch circuit for
an address buffer; a second switch circuit between the address buffer and the decoder circuit that selectively transmits an external address signal or the internal address signal to the decoder circuit; The internal address generating circuit comprises: an internal signal generating circuit for forming at least a signal for operating the internal address generating circuit and a control signal for the second switch circuit; and an input/output circuit having at least a data output function; It has a configuration in which the first address of the data to be read can be set, a register in which the final address of the data to be read can be set, and a comparison circuit for comparing the value of the register with the value of the internal address generation circuit. By stopping the generation of the internal address signal when the two values match, the desired number of bits of data is continuously transmitted from the input/output circuit from the desired address area of the memory array via the buffer register. 1. A semiconductor memory device characterized in that it can be read out manually. 2. The semiconductor memory device according to claim 1, wherein the internal address generation circuit is set to a predetermined initial state by a signal output from the internal signal generation circuit. 3. The initially set internal address generation circuit is counted up or down by an externally supplied signal or a clock signal from an internal oscillation circuit to form a continuously changing internal address signal. A semiconductor memory device according to claim 2, characterized in that it is configured as follows.