JPH0782751B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device which receives and holds an address signal from an address terminal and decodes an output of a counting means (hereinafter referred to as an address counter) capable of counting.

FIG. 1 shows a conventional synchronous semiconductor memory device having a structure of 1024 words × 4 bits. FIG. 2 is a timing chart of the semiconductor memory device shown in FIG. The operation of the semiconductor memory device shown in FIG. 1, particularly the read operation will be described below with reference to FIG.

FIG. 1 and FIG. 10 show address terminals, the signals of which are inputted to the address latch circuit 14. This latch circuit is a terminal (hereinafter ▲
▼ It is called a terminal. ) Latch the address information at the falling edge of the 12 signal. FIG. 2 shows address information inputted from the address terminal 10, and 22 shows a signal inputted to the terminal 12. The address information is ▲
▼ It is valid only for a certain period of time before and after the signal falls, and otherwise it may be high or low. The address information is transmitted from the latch circuit 14 to the row decoder 15 and the column decoder 16, and four memory cells in the memory cell array 17 are selected. Next, the storage information stored in the selected memory cell is output to the data input / output terminal 11 through the input / output circuit 16. Figure 2 24 shows this data input / output terminal.
11 shows the stored information output. Fig. 1 Terminal 13
R / W terminal, held high during read operation as shown by signal 23.

In such a conventional semiconductor memory device, when reading the storage information of several consecutive addresses, the address information must always be input to the address terminal 10 before reading the storage information of each address. did not become. Therefore, the input operation of the address information is complicated. Further, the conventional semiconductor memory device has the same drawbacks as the read operation even when the memory information is written in several consecutive addresses.

The present invention eliminates such drawbacks of the conventional semiconductor memory device. Therefore, an object of the present invention is to provide a memory in which a read operation or a write operation is performed when the stored information is continuously read by the memory cells of consecutive addresses, or when the stored information is continuously written to those memory cells. It is an object of the present invention to provide a semiconductor memory device capable of continuous read operation or write operation by designating only the head address of a cell.

According to a first aspect of the present invention, in a semiconductor memory device having an input / output circuit for writing or reading stored information stored in a memory cell array, a first control signal for controlling a timing for holding a start address of address information is input.
Input terminal, a second input terminal for inputting a second control signal for controlling an operating state and a standby state of the semiconductor memory device, and the address information based on the first and second control signals. The counter has a counting unit that holds the input, and a decoder that selects a predetermined memory cell of the memory array based on the address information output from the counting unit. On condition that the storage device is in the operating state, the first
The address information is input and held based on the timing control of the control signal, and the input and held address information is sequentially stepped up every time the second control signal changes.

Hereinafter, the present invention will be described in detail based on examples.

FIG. 3 shows an embodiment of the present invention. The same circuits as those in FIG. 1 are designated by the same reference numerals. FIG. 4 shows an embodiment of the address counter 31 of FIG. 3, and FIG. 5 is a timing chart of the address counter. FIG. 6 is a timing chart of the read operation of this embodiment. The operation of this embodiment will be described below with reference to these drawings.

When performing a read operation, the R / W terminal 13 is kept high as indicated by 61, and the signal 60 is input to the address terminal. The address information input to the address terminal is the address write enable bar ▲ ▼ terminal which is the first control signal.
At the rising edge of the signal 50 of 30, the address counter 31 is latched. Also, the second control signal ▲ ▼ signal 51 must be changed from high before the ▼ signal 50 rises to low. FIG. 6 shows that the address signal 60 is valid only for the address information for a certain time before and after the rising of the signal 50. In this way the address counter 31
The address information set in is input to the row decoder 15 and the column decoder 16. Thereafter, the address information is decoded, four memory cells are selected from the memory cell array 17, and the storage information is output to the data input / output terminal as shown in FIG.

To read the memory information of the next consecutive address,
First, ▲ ▼ terminal 12 is changed from low to high. At this time, the address counter 31 is updated. The signal 33 in FIG. 3 is the clock signal of the address counter 31. By holding the high level for a certain period of time and then making it low again, the stored information at the next address is read out to the data input / output terminal after a certain period of time. In this case, unlike reading the top address, it is not necessary to input address information to the address terminal 10, and the ▲ ▼ terminal is kept high.
The stored information after the third address can be read in the same manner as the reading of the next address. Also, regarding the write operation, R /
Other operations are exactly the same as the read operation except that the W terminal 13 is set to low and the stored information is input to the data input / output terminal.

FIG. 4 is an example of an address counter, and the figure shows a 3-bit counter. 32 and 33 are the same signals as 32 and 33 in FIG.

40 is a flip-flop that can be set and reset. The writing of address information to the flip-flop 40 is controlled by 32. When the third control signal, signal 32, is low, address information is written to flip-flop 40. 33 is a clock signal of this address counter, and 41, 42, 43 are output signals. 5 and 50 and 52 correspond to FIGS. 32 and 33, respectively, and 53, 54 and 55 are
Reference numeral 51, which corresponds to 41, 42, and 43, is a signal. In accessing the memory cell at the head address, a low pulse is input to the signal 50 in order to write the address information in the address counter. In accessing the memory cells at the next address and thereafter, since it is not necessary to write the address information in the address counter, the signal 50 is kept in the high state. This update of the address counter is performed at the rising edge of the signal line 51.

Examples of the present invention have been described below, but the present invention is not limited to these examples. In the example
Although only the 4K bit random access memory is mentioned, the present invention can be applied to a random access memory and a read only memory having a storage capacity other than 4K bits.

As described above, according to the present invention, when accessing several consecutive addresses, it is not necessary to input the address information prior to accessing each address, so that the input operation of the address information is greatly simplified. Has the effect. Moreover, any place can be designated as the head address.

Further, since not only the first control signal but also the second control signal is the input condition of the head address, there is no possibility of erroneous writing, and the signal that advances the counting means is the operating state of the semiconductor memory device. And the second control signal for controlling the standby state, there is also an effect that it is not necessary to newly provide a dedicated signal terminal for stepping the counting means. As described above, the semiconductor memory device of the present invention is much easier to use than the conventional semiconductor memory device.

[Brief description of drawings]

FIG. 1 shows a conventional semiconductor memory device. 10 …… Address terminal 11 …… Data input / output terminal 12 …… ▲ ▼ terminal 13 …… R / W terminal FIG. 2 is a timing chart of the semiconductor memory device of FIG. FIG. 3 is a diagram showing a semiconductor memory device according to an embodiment of the present invention. 31 …… Address counter 32 …… Control signal for inputting address information 33 …… Clock signal for address counter Fig. 4 shows an embodiment of the address counter. FIG. 5 is a timing chart of the address counter of FIG.

Claims (1)

[Claims] 1. A semiconductor memory device having an input / output circuit for writing or reading stored information stored in a memory cell array, wherein a first control signal for controlling a timing for holding a start address of address information is input. 1 input terminal, a second input terminal for inputting a second control signal for controlling an operating state and a standby state of the semiconductor memory device, and the address information based on the first and second control signals. And a decoder for selecting a predetermined memory cell of the memory array based on the address information output from the counting means, wherein the counting means has the second control signal On condition that the semiconductor memory device is in the operating state, the address information is input and stored based on the timing control of the first control signal. The semiconductor memory device is characterized in that the successively incremented address information the input held every time the second control signal changes.