JPH0443272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a video signal synthesis circuit that synthesizes three types of video input signals to be displayed on a cathode ray tube surface with a specified brightness.

(b) Background of the technology Display devices used in information processing systems are devices that display characters, symbols, and figures as visible images, and are input/output devices that facilitate information exchange between humans and machines.

Although liquid crystals, plasma panels, and the like are being put into practical use as display elements, cathode ray tubes (hereinafter referred to as CRTs) are currently the mainstay.

Conventionally, display devices have been used in special fields, but with the development of information processing systems, they have rapidly become popular and developed.

With the recent rapid progress in integrated circuit technology and the expansion of its range of applications, there has been an even stronger need to provide more reliable and less expensive display devices.

(c) Prior Art and Problems A conventional video signal synthesis circuit will be explained with reference to the drawings, taking a CRT video signal synthesis circuit as an example.

FIG. 1 shows a conventional video signal synthesis circuit for CRT.

In the figure, 1 is a transistor switching section with an inverter function, 2 is a video amplification section, 3,
4 is a brightness difference adjusting section, L1 is a wire, R1 to R8 are resistors, RV1 is a variable resistor, and TR1 to TR3 are transistors, respectively. Note that a, b, and c are input terminals, and input terminal a receives a predetermined brightness input signal (hereinafter referred to as input signal A), and input terminal b receives a high brightness input signal that is brighter than input signal A (hereinafter referred to as input signal B). d is a video signal output terminal;
+VB1 and +VB2 indicate power supply voltages, respectively.

In the circuit shown in FIG. 1, when input signal A and input signal B are input, the transistor switching section 1 is operated to switch, and the output is sent to the emitter of the transistor TR1 of the video amplification section 2 or the transistor TR2 of the brightness difference adjustment section 3. The video signal output is controlled by connecting each emitter current to the Also, when input signal C is input, resistor R
7 to the emitter of the transistor TR1 to control the video signal output. The brightness difference adjustment units 3 and 4 function to control the brightness difference between input signal A and input signal B.

Although the above circuit has a circuit configuration that has a stable track record, it requires a large mounting space because it requires a transistor element and a large number of resistors and capacitors for each input signal processing circuit. Furthermore, the large number of parts constituting the circuit increases the rate of occurrence of failures, and there is a problem in that there is a limit to the improvement in product reliability.

(d) Purpose of the Invention The purpose of the present invention is to provide a new video synthesis circuit that solves the above problems, and in particular, to realize a video signal synthesis circuit using general-purpose integrated circuit logic elements. The object of the present invention is to reduce the number of parts, improve the reliability of the circuit, and realize a small and inexpensive video signal synthesis circuit.

(e) Structure of the Invention The present invention provides a video amplification circuit for amplifying a video input signal to be displayed at a predetermined brightness on a cathode ray tube surface, wherein a first input terminal for inputting the video signal of the predetermined brightness has a first negative logic. A second input terminal connected to one input of the product element and inputting a high-intensity video signal that emphasizes a certain portion of the displayed image is connected to one input of the second NAND element, and a second input terminal is connected to one input of the second NAND element, and A third input terminal connected to the other input of the AND element and inputting the light pen video signal is connected to two inputs of the third NAND element, and a third input terminal is connected to the other input of the second NAND element. an output of the third NAND element is connected to two inputs of a fourth NAND element, and an output of the fourth NAND element is connected to the second input terminal. and a connection midpoint on the power supply side of a series circuit including three resistors connected between the power supply and the output of the third NAND element is connected to the output of the first NAND element. and is connected to the input of the video amplifier circuit, and the other connection midpoint of the series circuit made up of the three resistors is connected to the output of the second NAND element. It can be achieved.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of the video amplification circuit according to the present invention, where A shows a circuit diagram and B shows a waveform diagram.

In the figure, 5 is a switching circuit, 6 is a video amplifier circuit, 7 is a NAND element block, and R
9 to R16 are resistors, IC1 to IC4 are NAND elements, and TR4 is a transistor, respectively.

The same symbols as in Figure 1 indicate the same contents, and T0
~T5 is the waveform output period under the specified conditions, VO1~VO3
indicate the video signal output voltage, respectively.

In this embodiment, a switching circuit 5 performs a switching operation to output a signal to a video amplifier circuit 6 when input signals A, B, and C are input, and a CRT converts video signals having three types of brightness by signals from the switching circuit 5. A video amplifier circuit 6 outputs to a cathode or grid (not shown), and an open collector type NAND element integrated circuit that is located in the switching circuit 5 and performs a switching operation when input signals A, B, and C are input. It is composed of a NAND element block 7.

Three input signals, namely input signal A, input signal B, and input signal C, are connected to the NAND element block 7. Input signal A is a normal brightness signal for normal display, input signal B is a high brightness signal to emphasize a specific part displayed with the normal brightness signal, and input signal C is a high brightness signal for light pen detection. (the highest luminance signal among the three input signals) is inputted respectively. Each input signal A, B, C is IC1,
They are output from IC3 and IC4, respectively, and connected to the base of output transistor TR4 directly or via resistor R14 and variable resistor RV1.

Input signal A is connected to one input terminal of IC1, input signal B and the output of IC2 are connected to the other input terminal (input signal B and the output of IC2 are wired ANDed), and the logic of the input signal is It operates to take the product and minimize the phase shift. IC3
Input signal B is connected to one input terminal of , input signal C is connected to the other input terminal, and the input signal is operated to perform a logical product of the input signals and to minimize the phase shift. TR1 voltage amplifies the output from the NAND element block 7, and the voltage amplified output waveform is shaped by the coil L,1 and output to the cathode or grid (not shown) of the CRT.

The input level of each input signal A, B, and C is normally a transistor-transistor logic (TTL) high level "1", and becomes "0" when an image is displayed on a CRT (not shown).

Next, the operation of this embodiment will be explained based on FIG. 2B.

During the period T0 in which the input signals A, B, and C are all "1", the input signal A is at one input terminal of IC1, and the output signal and input signal B of IC2 are both at "1" at the other input terminal. ”, so “1” is input. Therefore, the output of IC1 becomes "0", the output transistor TR4 is cut off, and the collector potential of the output transistor TR4 becomes approximately +VB2.

Next, in the case of period T1 when only input signal A is “0”,
IC3 and IC4 outputs remain “0” and IC
Since the 2nd output also remains “1”, the IC2 output and
The other input of IC1 becomes "1" due to the wired AND of the inputs of IC3. That is, IC1 is “0”
The output becomes "1" by the AND of "1" and "1". The base voltage of output transistor TR4 at this time is
Assuming VT1, VT1≒R14・VB1/R13
+R14, and the voltage of VO1 appears at the collector of the output transistor TR4.

Next, in the case of period T2, input signals A and B are “0”,
This is the case when the input signal C is "1", the input of IC1 is "0" and "1", the input of IC3 is "0" and "1",
The inputs of IC4 are "1" and "1" (therefore, the output of IC2 is "1", and one input terminal of IC1 is "1").
"0" is input by wired AND of output "1" and IC3 input "0"), and IC1 and
The output of IC3 becomes "1" and the output of IC4 becomes "0". If the base voltage of the output transistor TR4 at this time is VT2, then VT2≒(R14+RV
1)・VB1/R13+R14+RV1 (However,
VT1<VT2), and the voltage of VO2 appears at the collector of the output transistor TR4.

Next, in the case of period T3, the input signals A, B, and C are "0", and the inputs of IC1, IC3, and IC4 are all "0" (therefore, the output of IC2 is "0"),
Therefore, all outputs are "1". If the base voltage of the output transistor TR4 at this time is VT3, then
VT3≒VB1 (however, VT1<VT2<VT3)
Therefore, the collector of output transistor TR4 is
The voltage of VO3 appears.

Next, in the case of period T4, input signals A and C are “0”
In this case, the inputs of IC1 and IC4 are both “0”,
The inputs of IC3 are "1" and "0", so the outputs are all "1", which is the same as in the period T3. Also, in the case of the period T5, all outputs are "1", which is the same as in the case of the period T3.

As seen in the above operation, if you want to use input signal A as a normal brightness signal and make a certain part high brightness, set input signal B to "0" to make the brightness high regardless of input signal A. It can be done. Similarly, input signal C can obtain higher luminance than input signal B, regardless of input signal A or input signal B. Note that by varying RV1, it is also possible to control the luminance difference between input signal A and input signal B.

Furthermore, in the video signal synthesis circuit of the present invention, the entire conventional circuit shown in FIG. 1 can be realized by using the NAND element block 7 of one general-purpose logic IC and a small number of other parts.

(g) Effects of the Invention As described above, according to the present invention, it is possible to use general-purpose integrated logic elements in place of conventional circuits using individual elements, and as a result, the number of parts can be reduced and the circuit This has the effect of improving the reliability of the circuit and realizing a small and inexpensive video signal synthesis circuit.

[Brief explanation of drawings]

FIG. 1 shows a conventional CRT video signal synthesis circuit, and FIG. 2 shows an embodiment of a video amplification circuit according to the present invention. In the figure, 1 is a transistor switching section, 2 is an image amplification section, 3 and 4 are brightness difference adjustment sections, and 5 is a transistor switching section.
is a switching circuit, 6 is a video amplifier circuit, and 7 is a switching circuit.
is a NAND element block, L1 is a wire ring, R1~
R16 is a resistor, RV1 is a variable resistor, TR1~
TR4 is a transistor, and IC1 to IC4 are NAND elements.

Claims (1)

[Scope of Claims] 1. In a video amplification circuit that amplifies a video input signal to be displayed at a predetermined brightness on a cathode ray tube surface, a first input terminal into which the video signal of the predetermined brightness is input is connected to a first NAND element. A second input terminal connected to one input and inputting a high-intensity video signal that emphasizes a certain portion of the displayed image is connected to one input of the second NAND element, and a second input terminal is connected to one input of the second NAND element, and a second input terminal is connected to one input of the second NAND element. A third input terminal is connected to the other input of the light pen video signal and is connected to the two inputs of the third NAND element, and is connected to the other input of the second NAND element. connected, an output of the third NAND element is connected to two inputs of a fourth NAND element, an output of the fourth NAND element is connected to the second input terminal, A connection midpoint on the power supply side of a series circuit including three resistors connected between a power supply and the output of the third NAND element is connected to the output of the first NAND element, and a video amplifier A video signal synthesis circuit characterized in that the other connection midpoint of the series circuit including the three resistors is connected to the input of the circuit and connected to the output of the second NAND element.