JPH0456366B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a pulse reproduction circuit corresponding to magnetization reversal suitable for digital magnetic storage devices such as magnetic disk devices and magnetic tape devices. [Background of the Invention] In a digital magnetic storage device, information is stored as the presence or absence of magnetization reversal 1 as shown in FIG. This magnetization reversal 1 is reproduced by a magnetic head as a waveform 2 having a peak corresponding to the magnetization reversal. To detect the peak of the reproduced waveform, there is a method of differentiating the reproduced waveform, converting the peak position to the zero cross point of the differential waveform 3, and obtaining the read pulse 4 corresponding to the peak of the reproduced waveform 2.
Conventionally widely used. For example, see IEICE Magnetic Recording Study Group Materials, MR-71-6. However, this method has the drawback that noise components at high frequencies are emphasized by the differentiating circuit, resulting in a reduction in S/N depending on the selection of the band. As a method to compensate for this drawback, as shown in FIG. 2, there is a method of using integration instead of differentiation and slicing at the center level of the integral waveform 5 to obtain the readout pulse 6. For example, materials from the Magnetic Recording Study Group of the Institute of Electronics and Communication Engineers
MR−77−46, IEEE Trans.on Mag, Vol.
MAG-17, No.6, pp.3352-3354, No.
See VEMBER, 1981, etc. In this integration method,
Although it has the advantage that the S/N ratio is better than the differential method, it has the disadvantage that reading errors are likely to occur due to DC drift of the circuit because it includes an integrating circuit. [Object of the Invention] An object of the present invention is to provide a magnetization reversal pulse regeneration method using a stable integration method, eliminating the influence of DC drift of the circuit. [Summary of the invention] In the present invention, a PLL (Phase
This method uses the output of the phase comparator (Locked Loop) to remove the effects of circuit drift, etc. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIG. The signal read out by the magnetic head 7 is amplified by a regenerative amplifier 8 and sent to a magnetization reversal pulse reproducing circuit 31.
pulsed at The read pulse 6 is
The signal is input to the PLL circuit 30, which generates a discrimination window 19 synchronized with the read pulse 6. The readout pulse 6 is sent to the discrimination circuit 1 along with the discrimination window 19.
2, and is transferred to the host model together with the discrimination data 28 and clock 29 which are the outputs of the discrimination circuit. Here, the regenerative amplifier 8 may be a linear amplifier, but may also have the function of a waveform processing circuit that sharpens the regenerated waveform, such as a widely known pulse slimming circuit or waveform equalization circuit. The PLL circuit 30 is widely used for discrimination in digital magnetic recording devices, and includes a discrimination window 19, a phase comparator 16 that detects the phase difference with the read pulse 6, and a long period from the phase detection output of the phase comparator. It consists of a low frequency generator 17 for obtaining an output corresponding to the average phase shift at , and a voltage controlled oscillator 18 whose oscillation frequency changes compared to the input DC level. The configuration and operation of the magnetization reversal pulse regeneration circuit 31, which is the main part of the present invention, will be described with reference to FIGS. 3 and 5. The output of the regenerative amplifier 8 passes through the integrating circuit 9,
After being waveform-shaped by a comparator 10, it is pulsed 6 by a pulsing circuit 11. Here, integral waveform 5
When a center level shift occurs due to circuit drift or the like, correction is applied to the slice level 32 of the comparator 10 in order to eliminate the influence of the shift. Information for correction is obtained by comparing the frequency rising signal 24 and frequency falling signal 25, which are the outputs of the phase comparator 16 in the PLL circuit 30, with gate signals 22 and 23 that identify the direction of the slope of the integral waveform 5. The slice level increase signal 20 and level decrease signal 2 obtained by the slice level comparison circuit 15 are
1 is obtained by passing it through a low frequency filter 13. FIG. 4 shows an embodiment of the slice level comparison circuit 15 and the integral waveform slope identification circuit 14. Using this figure and Figures 3 and 5,
The slice level correction operation will be explained. As mentioned above, the slope identification circuit 14 detects the "zero" of the integral waveform 50.
This is a circuit for detecting the direction of the slope at the cross point, and consists of two comparators 141 and 142. Both inputs are reproduced waveforms 2, and positive and negative slice levels 26 and 27 are applied to each input. When the slope of the integral waveform 5 is positive, the pulse on the ten side of the reproduced waveform 2 is sliced at the slice level 26, and a gate signal 22 is generated from the comparator 141 indicating that the slope of the zero crossing point is positive, and the slope is Similarly, if it is negative, gate signal 2
3 is generated from comparator 142. If there is no drift in the integral waveform 5 and the readout pulse 6 can be reproduced correctly at the zero cross point (in the case of 2 bits on the left side of FIG. 5), the readout pulse 6 is located at the center of the discrimination window 19, so phase comparison is possible. There are no outputs 24, 25 of the device 16. Therefore, no level correction is performed. Next, consider the case where the integral waveform 5 is shifted downward as shown in the center 2 bits of FIG. In this case, both the left and right read pulses are shifted behind and before the original zero-crossing point, respectively. Therefore, as the output of the phase comparator 16, a frequency drop signal 25 and a frequency rise signal 24 equal to the phase difference between the center of the discrimination window and the read pulse are obtained corresponding to the left and right read pulses. Conversely, when the integral waveform 5 shifts upward (in the case of 2 bits on the right side in FIG. 5), a frequency increase signal 24 and a frequency decrease signal 25 are obtained corresponding to the left and right read bits, respectively. Table 1 shows how to obtain the level drop signal 21 for the center 2 bits in FIG. 5 and the level increase signal 20 for the right 2 bits from the output of the phase comparator 16 obtained as described above. It is sufficient to construct a logic circuit that satisfies the relationship.

〔Effect of the invention〕

According to the present invention, since problems such as drift of the integrating circuit can be eliminated, a magnetization reversal pulse reproducing circuit using the integrating circuit can be realized.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram for explaining the magnetization reversal pulse regeneration method using a differentiating circuit, Fig. 2 is a waveform diagram for explaining the magnetization reversal pulse regeneration method using an integrating circuit, Figs. The figure is a block diagram of one embodiment of the present invention, and FIG. 5 is a diagram showing waveforms of each part thereof. 7...Magnetic head for recording and reproduction, 8...Reproduction amplifier, 30...Phase Locked Loop, 16...
Phase comparator, 31...Magnetization reversal pulse regeneration circuit,
9...Integrator circuit, 10...Comparator, 11...
...Pulsing circuit, 14... Integral waveform slope identification circuit, 15... Slice level comparator, 13,1
7...Low frequency generator, 18...Voltage controlled oscillator, 1
2...discrimination circuit.

Claims (1)

[Claims] 1. An integrating circuit that integrates the magnetization reversal signal, a comparator that compares the output of the integrating circuit with a reference level, a pulsing circuit that pulsates the output of the comparator, and oscillates in synchronization with the output of the pulsing circuit. 1. A magnetization reversal pulse regeneration method comprising: an oscillator; the reference level of the comparator is corrected in accordance with the phase difference between the output of the oscillator and the output of the pulsing circuit.