JPH0458675B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a memory control circuit, a microprocessor incorporating the same, a CRT control device, and an integrated circuit device, and particularly relates to a device that can directly control a dynamic RAM. [Prior Art] FIG. 1 shows the configuration of a system that uses dynamic RAM as a storage device. integrated circuit device 10,
Clock generator 11, timing signal generator 1
2, address multiplexer 13, memory 14,
Consists of. Integrated circuit device 10 controls a large memory via a 16-bit address bus and an 8-bit data bus. Typical integrated circuit devices that handle such large-capacity memories include various microprocessors and CRT control devices.
A clock generator 11 generates a reference clock for each section. The timing signal generator 12 generates dynamic RAM control signals, RAM address multiplex timing signals, and the like. The address multiplexer 13 multiplexes a 16-bit address signal into a row address and a column address of the dynamic RAM and outputs it onto eight RAM address lines. Memory 14 consists of eight 64 kilobit dynamic RAMs. Here, in the case of static RAM, taking a 64 kilobit RAM as an example, a 16-bit address signal is output on 16 address lines. Therefore, when switching to 16 kilobit static RAM, predetermined address bits need only be fixed to predetermined values. However, in the case of dynamic RAM, as shown above, in the case of 64 kilobits,
The 16-bit address signal is multiplexed into the row address and column address of the dynamic RAM, and eight
It is output on the RAM address line. For this reason,
When switching to 16 kilobit dynamic RAM, you must set whether to multiplex a given address or not. FIG. 2 shows an operating time chart of the dynamic RAM. Row addresses (RA) and column addresses (CA) are time-division multiplexed and placed on the address lines. As control signals, row address strobe (RAS), column address strobe (CAS),
Write control signal (WE) is required. The timing of this control signal varies depending on the type of RAM used. Furthermore, the pattern for multiplexing addresses also differs depending on the type of dynamic RAM. For example, in the case of a 16 kilobit dynamic RAM, a 14-bit address signal is multiplexed and supplied to seven signal lines. In the case of a 64 kilobit dynamic RAM, a 16-bit address signal is multiplexed and supplied to eight signal lines. In this way, highly integrated dynamic RAM
By using this, the number of memory chips can be reduced, but circuits such as a timing signal generator 12 and an address multiplexer 13 are required. Conventionally, these circuits were constructed from individual components, which resulted in an increased number of components and a more complex system. Another disadvantage of dynamic RAM is that the memory is temporary and must be refreshed within a certain period of time. For this reason,
Normally, it is necessary to provide a refresh address counter and a refresh timing control circuit. Conventionally, devices that incorporate a refresh address counter inside the integrated circuit device 10 and devices that integrate a refresh address counter and an address multiplexer have been announced. There are also RAM devices that include a refresh address counter. However, in either case, since only a refresh address counter is built-in, an external circuit for controlling refresh timing is required. Generally, when refreshing, each refresh address must be set consecutively. That is, refresh is performed by continuously changing row addresses column by column. Based on the above conditions, when changing the type of dynamic RAM, the output state of the address signal unique to each dynamic RAM is determined. Therefore, in order to determine the output state of the address,
All that is required is to define mode information and determine the output state of the address based on this mode information. [Object of the Invention] An object of the present invention is to provide a memory control circuit that can be directly connected to various dynamic RAMs in order to reduce the number of system parts, and various integrated circuit devices incorporating the same. [Summary of the Invention] The feature of the present invention is that the dynamic RAM to be connected
The reason is that addresses are multiplexed in accordance with mode information indicating the type of address. [Embodiments of the Invention] Examples of the present invention will be described in detail below based on the drawings. FIG. 3 shows an integrated circuit device 30 according to an embodiment of the present invention.
and an example of a system configuration that uses it to control dynamic RAM. The integrated circuit device 30 includes a timing signal generator 31, an address multiplexer 32, a mode register 33, and a refresh address counter 34. The system is simple, consisting of an integrated circuit device 30, a clock generator 11, and a memory 14. The timing signal generator 31 generates a dynamic RAM control signal and an address selection signal from an externally input reference clock signal (CLK). Dynamitsuku
RAM control signals include a row address strobe (RAS), a column address strobe (CAS), and a write control signal (WE), which are output from the output terminal of the integrated circuit device 30. Address selection signals include a row address selection signal (RA), a column address selection signal (CA), and a refresh address selection signal (REF). The address multiplexer 32 is a 16-bit memory address (A0 to 15).
and 8-bit refresh address (R0~7)
is input, the address is switched and controlled according to the timing of the address selection signals RA, CA, and REF, and output to the output terminals (X0 to 7). Note that the output terminal may be an input/output terminal. The mode register 33 is a register that determines the address multiplex format, and in this embodiment is a 1-bit register that specifies either a mode for connecting a 16 kilobit RAM or a mode for connecting a 64 kilobit RAM. The refresh address counter 34 is a refresh address counter for dynamic RAM.
It manages 8 bits of address and has the function of adding +1 to each input of the refresh address selection signal (REF). According to this embodiment, the timing generation circuit 31,
By incorporating the address multiplexer 32 and the refresh address counter 34 inside the integrated circuit device 30, the number of components in the system can be significantly reduced. Also, the address multiplexer 3 is controlled by the mode register 33 and its output signal (M).
Since the configuration is such that the two functions can be switched, it is possible to support multiple types of dynamic RAM (in this embodiment, two types, 16 kilobit RAM and 64 kilobit RAM). FIG. 4 shows a time chart of dynamic RAM control signals in the embodiment of FIG. Row address signal (RAS), column address signal (CAS),
Write control signal (WE), RAM address (X0~
7) is shown in parallel with the reference clock (CLK). Parameter a shown in the figure,
By using b, c, and d, the timing can be set programmably using the period of the reference clock (CLK) as a unit. Therefore, it is possible to support various dynamic RAMs with different operation timings. FIG. 5 shows the circuit of address multiplexer 32 in detail. Address selection timing signal
The addresses to be output to the output terminals (X0 to X7) are appropriately selected by RA, CA, and REF. Furthermore, two types of multiplex modes are selected by the mode signal (M). Table 1 summarizes the address bits output at each timing.

〔Effect of the invention〕

According to the present invention, the number of components for a system configuration can be reduced by using a memory control circuit that can accommodate a plurality of dynamic RAMs and various integrated circuit devices incorporating the same.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a system configuration using a conventional dynamic RAM, FIG. 2 is an operation time chart of the dynamic RAM, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of the address multiplexer of the present invention. 30... integrated circuit device, 31... timing signal generator, 32... address multiplexer, 3
3...Mode register, 34...Refresh
Address counter.

Claims (1)

[Scope of Claims] 1. In a memory control circuit that multiplexes information on a plurality of address bits for driving a dynamic RAM into row addresses and column addresses in a time-division manner, 1. A memory control circuit comprising means for selecting whether to multiplex or not multiplex a plurality of address bits in accordance with mode information indicating an address output state. 2. In a memory control circuit that multiplexes information on a plurality of address bits to drive a dynamic RAM into a row address and a column address in a time-division manner, 1. A memory control circuit comprising means for selecting whether to multiplex address bits or multiple other address bits in accordance with mode information indicating an output state of an address. 3 In an integrated microprocessor that multiplexes the information of multiple address bits to drive a dynamic RAM into row addresses and column addresses by time division and outputs the same from an output terminal or an input/output terminal, the above The above address is set according to the mode register provided inside the microprocessor or the mode information indicating the output state of the above address from the outside.
A microprocessor comprising a built-in memory control circuit that selects whether a predetermined plurality of address bits among the bits are multiplexed and output from the terminal, or are not multiplexed and output from the terminal. 4. In an integrated microprocessor that multiplexes the information of multiple address bits to drive a dynamic RAM into row addresses and column addresses by time division and outputs it from an output terminal or an input/output terminal, the above The above address is set according to the mode register provided inside the microprocessor or the mode information indicating the output state of the above address from the outside.
It is characterized by a built-in memory control circuit that selects whether a predetermined plurality of address bits among the bits are multiplexed and output from the above terminal, or a plurality of other address bits are multiplexed and output from the above terminal. microprocessor. 5 An integrated CRT that multiplexes the information of multiple address bits to drive dynamic RAM into row addresses and column addresses by time division and outputs the multiplexed information from an output terminal or an input/output terminal.
In the control device, a predetermined plurality of address bits among the address bits are multiplexed according to a mode register provided inside the CRT control device or mode information indicating an output state of the address from the outside. A CRT control device comprising a built-in memory control circuit that selects whether to output from the above-mentioned terminal or to output from the above-mentioned terminal without multiplexing. 6 An integrated CRT that multiplexes the information of multiple address bits to drive dynamic RAM into row addresses and column addresses by time division and outputs the multiplexed information from an output terminal or an input/output terminal.
In the control device, a predetermined plurality of address bits among the address bits are multiplexed according to a mode register provided inside the CRT control device or mode information indicating an output state of the address from the outside. A CRT control device comprising a built-in memory control circuit that selects whether to output from the above terminal or multiplex other address bits and output from the above terminal. 7 In an integrated circuit device that multiplexes the information of multiple address bits for driving a dynamic RAM into row addresses and column addresses by time division and outputs the same from an output terminal or an input/output terminal, the above A predetermined plurality of address bits among the address bits are multiplexed and output from the terminal according to mode information indicating the output state of the address from a mode register provided inside the integrated circuit device or from the outside. 1. An integrated circuit device comprising a built-in memory control circuit that selects whether to output from the terminal without multiplexing or to output from the terminal without multiplexing. 8. The integrated circuit device according to claim 7, characterized in that it incorporates a memory control circuit provided with a means for counting the refresh rate of the dynamic RAM. 9. An integrated circuit device according to claim 7, characterized in that it incorporates a memory control circuit provided with means for generating a row address strobe signal and a column address strobe signal for a dynamic RAM. 10 In an integrated circuit device that multiplexes information on a plurality of address bits for driving a dynamic RAM into row addresses and column addresses by time division and outputs the same from an output terminal or an input/output terminal, the above A predetermined plurality of address bits among the address bits are multiplexed and output from the terminal according to mode information indicating the output state of the address from a mode register provided inside the integrated circuit device or from the outside. 1. An integrated circuit device comprising a built-in memory control circuit for selecting whether to multiplex address bits or multiplex other address bits and output them from the terminal. 11. An integrated circuit device according to claim 10, comprising a built-in memory control circuit provided with means for counting refresh addresses of a dynamic RAM. 12. An integrated circuit device according to claim 10, characterized in that it incorporates a memory control circuit provided with means for generating a row address strobe signal and a column address strobe signal for a dynamic RAM.