JPH046092B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a field effect transistor in a compound semiconductor integrated circuit, and particularly to a field effect transistor having a structure that suppresses the inflow of carriers caused by the incidence of alpha rays. Regarding.

[Conventional technology]

Traditionally, GaAs MESFETs (Metal
Regarding structures that suppress the inflow of carriers caused by the incidence of alpha rays in Semiconductor Field Effect Transistors, see, for example, IEE, Electron Device Letters,
E.D.L. Volume 7, Number 6 (1986)
Pages 396 to 397 (IEEE ELECTRON
DEVICE LETTERS, VOL.EDL-7, No.6,
(1986) pp. 396-397).

[Problem that the invention seeks to solve]

The above-mentioned conventional technology suppresses the inflow of carriers into the GaAs MESFET when α rays are incident on the MESFET. i.e. GaAs MESFET,
Alternatively, when alpha rays are incident near the FET, the generated carriers lower the potential barrier between the drain and source. Therefore, the injection of electrons from the source is promoted, and several times as many carriers as those generated by the incidence of α-rays flow into the drain. In the above-mentioned conventional technology, a P layer is buried under the FET to increase the potential barrier between the drain and the source, thereby suppressing the inflow of carriers into the drain.

By the way, it is necessary to provide a pad part on the gate electrode of the FET in order to make contact with the wiring metal. In the cross-sectional view of the conventional FET shown in FIG. 2, if the P layer 11 is also provided under the pad portion of the gate electrode 1, the metal
A Schottky diode is formed by the layers, α
Carriers generated by the incident radiation diffuse or drift and flow into the gate through this diode (indicated by arrows in FIG. 2). Since the above conventional technology does not take this point into consideration,
SRAM ( Static R) using such FET
When alpha rays are incident, the generated carriers flow into the gate electrode of the FET and the gate potential fluctuates greatly , potentially destroying the stored information held in the memory cell ( There was a problem with soft errors caused by alpha rays.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a field effect transistor with high resistance to alpha rays.

[Means for solving problems]

The above object is achieved by providing a structure having a high resistance material layer in contact with the lower part of the pad portion of the gate electrode of the FET.

More specifically, as the high-resistance material layer, an insulating layer, a depleted semiconductor layer, a high-resistance semiconductor layer compensated by a deep impurity level, a semi-insulating substrate, or the like is used.

[Effect]

By having a high-resistance material layer in contact with the lower part of the pad portion of the gate electrode, this layer does not allow carriers to pass through, so carriers generated in the substrate due to the incidence of alpha rays flow into the gate through the pad portion of the gate. This can be prevented. More specifically, it is as follows.

α rays incident on a GaAs substrate generate about 160 fc of holes and electrons. These carriers recombine and are lost in the substrate over time, but in the meantime they diffuse or drift within the substrate. α rays are transmitted to the pad part of the gate electrode of the FET,
Or if the carrier is incident near the pad portion of the gate electrode, the carrier is prevented from flowing into the gate electrode through the pad portion because of the high resistance material layer that does not allow carriers to pass through. Then,
Fluctuations in the FET gate potential can be suppressed,
When such a FET is used in an SRAM, soft errors due to incidence of alpha rays can be suppressed.

[Example] Reference Example 1 Hereinafter, the first reference example related to the present invention will be referred to as the first reference example.
This will be explained with reference to FIG. FIG. 1 is a cross-sectional structural diagram of a field effect transistor, and FIG. 3 is a view of the field effect transistor viewed from above the substrate. A P-type semiconductor layer 11, an n-type active layer 7, and an n ⁺ layer 3 are formed on a semi-insulating GaAs substrate 6 by ion implantation and a subsequent high-temperature heat treatment process. Any of Be, Mg, C, and Zn may be used for ion implantation of the P-type semiconductor layer 11, and the implantation energy is equal to that of the n-type active layer 7.
Although it depends on the formation conditions of the n ⁺ layer 3, it is usually 10keV~
The dose is selected within the range of 400 keV, and the dose depends on the implantation energy, but is usually selected within the range of 10 ¹¹ cm ^-2 or more. High temperature heat treatment is usually 700℃~850℃
Perform at a temperature of °C. Next, insulator film 2 is
It is formed in the area below the pad of the gate electrode by CVD ( Chemical Vapor Deposition ) method. This insulating film is the above-mentioned high-resistance material layer. As the insulating film 2, any of SiO ₂ , SiN ₄ , AlN, and Al ₂ O ₃ may be used. Thereafter, a gate metal 1, SiO ₂ film 8, source and drain electrodes 4, and wiring metal 9 are formed by the usual method.

According to this reference example, the area of the Schottky diode formed by direct contact between the pad portion of the gate electrode 1 and the P-type semiconductor 11 is significantly increased by sandwiching the insulating layer 2 between them. can be reduced to Therefore, carriers generated by α rays can be prevented from flowing into the gate electrode as described above. Furthermore, gate leakage current due to reverse leakage current of the Schottky diode can be significantly suppressed.

Example 1 Next, a first example of the present invention will be described using FIG. 4. The difference from the first reference example is that the insulator layer 2
The P-type semiconductor layer 11 is not selectively formed under the pad of the gate electrode 1, and the depleted P layer 12 is formed deeper than the active layer under the pad. This depleted P layer is the above-mentioned high resistance material layer. The depleted P layer 12 is
It is formed by ion implantation of Be, Mg, C, or Zn and a high-temperature heat treatment process. The implant energy is usually selected within the range of 10 keV to 400 keV, and the dose depends on the implant energy to satisfy the conditions for complete depletion, but is usually 10 ^{to 13} cm.
Select within the range of ^-2 or less. Depleted p-layer 1
By providing layer 2 deeper than the active layer, a thick depletion layer is formed below the pad of gate electrode 1, effectively blocking the inflow of carriers.

Example 2 A second example of the present invention will be described using FIG. 5. The difference from the first reference example is that the insulating layer 2 is omitted, and the high-resistance semiconductor layer 10 compensated by a deep impurity level is provided below the pad of the gate electrode 1 deeper than the active layer. The high resistance semiconductor layer compensated by this deep impurity level is the above-mentioned high resistance material layer. The semiconductor layer 10 has H,
It is formed by ion implantation of any one of O, V, Au, Cu, Fe, and Cr. The implantation energy is usually selected within the range of 10 keV to 400 keV, and the dose amount depends on the implantation energy in order to satisfy the conditions for completely compensating the P-type semiconductor layer 10 and making it semi-insulating. Usually selected within the range of 10 ¹¹ cm ^-2 or more. By providing the semi-insulating semiconductor layer 10 deeper than the active layer, carriers are effectively prevented from flowing into the pad portion of the gate electrode 1.

Reference Example 2 A second reference example related to the present invention will be explained using FIG. 6. The difference from the first reference example is that the insulator layer 2 is omitted, and there is a P layer below the pad of the gate electrode 1.
The point is that the type semiconductor layer 11 is not selectively formed.
In other words, the lower part of the pad of gate electrode 1 is semi-insulating.
Since it is in contact with the GaAs substrate 6 and this substrate becomes a high-resistance material layer, it is possible to prevent the inflow of carriers.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to prevent carriers generated when α rays are incident from flowing into the pad portion of the gate electrode, and the resistance to α rays is increased compared to conventional field effect transistors. be able to.

[Brief explanation of drawings]

Figure 1 shows a first reference example related to the present invention.
Cross-sectional view of FET, Figure 2 is cross-sectional view of conventional FET,
FIG. 3 is a plan view of the FET of the first reference example, FIGS. 4 and 5 are cross-sectional views of the FET of the first and second embodiments according to the present invention, and FIG. 6 is related to the present invention. FIG. 3 is a cross-sectional view of a second reference example FET. 1... Gate electrode, 2... Insulator layer, 3... n ⁺ layer,
4... Source, drain electrode, 6... Semi-insulating GaAs
Substrate, 7... N-type active layer, 8... SiO ₂ film, 9... Wiring metal, 10... Semiconductor layer compensated by deep impurity level, 11... P-type semiconductor layer, 12... Depleted P layer.

Claims (1)

[Claims] 1 At least a semi-insulating compound semiconductor substrate,
a first semiconductor region having an n-type and comprising source and drain regions formed spaced apart within the surface of the substrate and an active layer formed between the source and drain regions; A second semiconductor region having p-type formed in contact with the first semiconductor region at a lower portion thereof.
A field effect transistor comprising a semiconductor region and a gate electrode formed on the active layer,
A field effect transistor characterized in that it has a high resistance material layer that is in contact with the lower part of the pad portion of the gate electrode and is formed deeper within the surface of the substrate than the depth of the active layer.