JPH0473359B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a color video signal processing circuit suitable for application to a VTR. BACKGROUND ART AND PROBLEMS There are cases where color video signals are played back by a VTR with a slight deviation from the standard signal period. In other words, when a tape with a playback time of, say, 60 minutes in standard mode is played back at variable speeds within a range of about 60 minutes ± 1 minute, the field sequentiality of the playback signal from the VTR will match the standard of the reference signal at a period of several tens of fields. field sequentiality does not match. Therefore, in the past, such a color video signal was passed through a time base collector/frame synchronizer using a conventional 1-frame memory, and the reproduced color video signal was repeated in units of 1 field, thinned out, and the phase of the carrier color signal was processed. Through inversion processing, the format of the reproduced color video signal is made to conform to the format of a standard color video signal. However, since these processes are performed at a cycle of several tens of fields, the chroma inversion circuit, which is made up of a two-dimensional filter that operates at 1/2 duty, causes resolution degradation and unnatural momentary image movements on the screen. This is a practical problem. OBJECTS OF THE INVENTION The present invention provides a method for eliminating resolution deterioration and image quality deterioration when the field sequentiality and the phase of the carrier color signal are deviated from the reference field sequentiality and the reference phase of the carrier color signal, respectively. This paper attempts to propose a color video signal processing circuit that can correct each of these deviations. Summary of the Invention A color video signal processing circuit according to the present invention includes a first comparison circuit that compares the field sequentiality of an input decoded video signal with the field sequentiality of a reference signal, and a carrier color signal of the input decoded video signal. a second comparison circuit that compares the phase of the carrier color signal of the reference signal with the phase of the carrier color signal of the reference signal; and first and second decoded video signals to which the input decoded video signal is input and which have a time difference of one frame from each other due to delay processing. a delay means for outputting the first and second decoded video signals from the delay means, a motion detection circuit for detecting the magnitude of movement of the video signal; A first phase inversion circuit to which a video signal is supplied, inverts the phase of a carrier color signal of a first decoded video signal using the frame correlation of the video signal, and outputs the first decoded video signal; a second phase inversion circuit to which the decoded video signal is supplied, and which inverts the phase of the carrier color signal of the first decoded video signal using the line correlation of the video signal and outputs the inverted signal; and a first phase inversion circuit. a synthesis circuit that synthesizes the output video signal of the second phase inversion circuit and the output video signal of the second phase inversion circuit at a ratio according to the detection result of the motion detection circuit;
The first decoded video signal outputted from the delay means and the output video signal of the synthesis circuit are supplied to a switching circuit that selectively outputs these signals, and a first comparison circuit and a second comparison circuit. and a control circuit that controls the delay means and the switching circuit based on the comparison result,
When the field sequentiality of the input decoded video signal and the field sequentiality of the reference signal do not match, the delay circuit adjusts the output timing of the input decoded video signal by 1 compared to when they match. The switching circuit is controlled by a control circuit so that the carrier color signal of the input decoded video signal matches the phase of the carrier color signal of the reference signal, and is supplied from the delay means. A first decoded video signal is output, and a composite video signal supplied from the combining circuit is output when the phase of the carrier color signal of the input video signal and the phase of the carrier color signal of the reference signal do not match. be controlled by the control circuit. According to the present invention, when the field sequentiality and the phase of the carrier color signal are deviated from the reference field sequentiality and the reference phase of the carrier color signal, respectively, it is possible to correct the problem without causing resolution deterioration or image quality deterioration. , it is possible to obtain a color video signal processing circuit that can correct each of the deviations. Embodiment An embodiment of the present invention will be described below with reference to FIG. Reference numeral 1 denotes an input terminal to which an NTSC color video signal, which is a reproduction signal from an Ω-wound VTR such as an SMPTE type C-type VTR, is supplied. This color video signal is a signal obtained by, for example, reproducing a tape with a playback time of 60 minutes in standard mode at variable speed within a range of about 60 minutes±1 minute using a dynamic tracking method. 2 is a frame memory in which the color video signal from the input terminal 1 is written and stored, and from which it is read out. 3 is a control circuit that controls the read address of this memory 2. FIG. 2 schematically shows this memory 2, and this memory 2 has memory sections 2A and 2B that store signals of each field of a color video signal. In FIG. 2, W indicates a write signal, and the write timing rotates clockwise, for example. According to the rotation of the write timing of the write signal W, the stored contents of the memory 2 are rewritten.
R _1a , R _2a ; R _1b , R _2b represent read signals, each of which rotates clockwise with the timing of the read signal W while maintaining a predetermined phase relationship with respect to the write signal W. The read timing of the read signal R _1a is nH later than the write timing of the write signal W (where n = 1, 2, 3, ..., H is the horizontal period), and the read timing of the read signal R _2a is nH later than the write timing of the write signal W. , nH before the write timing of the write signal W. Also, the read timing of the read signal R _1b is 1 field period - nH before the write timing of the write signal W, and the read timing of the read signal R _2b is 1 field period + nH before the write timing of the write signal W.
In front. For example, n is 10. Then, read signals (color video signals) R ₁ and R ₂ are output from the frame memory 2, and one read signal R ₁
is either one of the read signals R _1a or R _1b ,
The other read signal R ₂ is one of the read signals R _2a and R _2b . The selection of such a readout signal is
Controlled by address control circuit 3. Read signal R ₂ (R _2a or R _2b ) from frame memory 2
is supplied to a delay circuit 4 having a delay amount of 2nH (hereinafter simply referred to as 2nH delay circuit) 4 and delayed. Color video signal R ₂ ′ (R ′ _2a or
R′ _2b ) is a signal delayed by exactly one frame from the color video signal R ₁ . Reference numeral 5 generally indicates a phase inverting circuit for inverting the phase of a carrier color signal of a color video signal, which will be described below. The color video signal _R1 is supplied to a phase inversion circuit 6 which inverts the phase of the carrier color signal by line correlation. The color video signals R ₁ , R ₂ ' are supplied to a phase inversion circuit 7 which inverts the phase of the carrier color signal by frame correlation. The color video signals R ₁ and R ₂ ' are supplied to a motion detection circuit 8 that detects screen motion. The respective output signals of both phase inversion circuits 6 and 7 are supplied to a synthesis circuit 9 and synthesized, and the synthesis ratio is controlled by the detection output from the motion detection circuit 8. In this case, the synthesis circuit 9 is configured such that the more violent the movement, the greater the proportion of the output signals from the phase inversion circuit 6, and the quieter the movement, the greater the proportion of the output signals from the phase inversion circuit 7. The synthesis ratio of is controlled. 10 is a line addition circuit for line addition of the luminance signal of the color video signal;
R ₁ is supplied. The color video signal R ₁ and the output of the combining circuit 9,
The output of the line adder circuit 10 is supplied to a switching circuit 11, these signals are switched, and one of the signals is outputted to an output terminal 12. A comparison circuit 13 compares the field sequentiality of the input color video signal and the phase of the carrier color signal from the input terminal 1 with the reference field sequentiality of the reference signal and the reference phase of the carrier color signal from the input terminal 14, respectively. This will be explained below. The color video signal from the input terminal 1 is supplied to a comparator circuit 15 that compares odd and even fields, and the color video signal is sent to the input terminal 14.
The reference signal from the reference field is compared with the odd-even field. Comparison circuit 1 in which the color video signal R ₁ from the frame memory 22 compares the phase of the carrier color signal
6 and is compared with the reference phase of the carrier color signal of the reference signal from the input terminal 14. The comparison outputs from the comparison circuits 15 and 16 are supplied to the control circuit 17, and the address control circuit 3, line addition circuit 10 and switching circuit 1 are controlled by the control signals from the control circuit 17.
1 is controlled. Reference numeral 18 denotes a synchronization signal generation circuit which receives the reference signal from the input terminal 14, generates an advanced synchronization signal based on the reference signal, and supplies it to the VTR. Next, a specific example of the configuration of each circuit of the processing circuit shown in FIG. 1 will be explained. First, with reference to FIG. 3, the phase inversion circuit 6 for carrier color signals based on line correlation will be described. A color video signal R ₁ is supplied to the input terminal 21 . This color video signal _R1 has a delay amount of
1H delay circuit (hereinafter simply referred to as 1H delay circuit) 2
2 and delayed by 1H. 1H delay circuit 22
Based on the color video signal of Y±
C (where Y indicates a luminance signal and C indicates a carrier color signal). The signal Y±C from the 1H delay circuit 22 is supplied to the next-stage 1H delay circuit 23 and delayed by 1H, thereby obtaining the signal Y〓C. In the synthesizer 24, the signal R ₁ (=Y〓C) from the input terminal 21 and the signal Y〓C from the 1H delay circuit 23 are added to obtain signal 2 (Y〓C), and this Signal 2 (Y〓C) is supplied to an attenuator 25 and attenuated to 1/2 to obtain signal Y〓C.
In the synthesizer 26, the signal Y≓C from the attenuator 25 is subtracted from the signal Y±C from the 1H delay circuit 22, and the subtraction output is supplied to the bandpass filter 27. ±2C can be obtained.
In the synthesizer 28, the signal ±2C from the bandpass filter 27 is subtracted from the signal Y±C from the 1H delay circuit 22, and the signal Y〓C is sent to the output terminal 29.
is output. The color video signal Y〓C from the output terminal 29 is obtained by inverting the phase of the carrier color signal ±C of the color video signal Y±C from the 1H delay circuit 22. Next, with reference to FIG. 4, the carrier color signal phase inversion circuit 7 based on frame correlation will be described.
Color video signals R ₁ from input terminals 31 and 32,
R ₂ ' are supplied to H delay circuits 33 and 34, respectively, and are delayed. Based on the signals from the 1H delay circuits 33 and 34, they are expressed as Y±C and Y〓C, respectively.
Incidentally, these 1H delay circuits 33 and 34 are provided in association with the 1H delay circuit 22 in the phase inversion circuit 6 of FIG. In the synthesizer 35, 1H
By subtracting the signal Y〓C from the 1H delay circuit 34 from the signal Y±C from the delay circuit 33 and supplying the subtracted output to the bandpass filter 36, a signal ±2C is obtained. In the synthesizer 37, the signal from the 1H delay circuit 33 is passed through the bandpass filter 36.
The output signal Y〓C is obtained at the output terminal 38 by subtracting the signal ±2C. The color video signal Y〓C from the output terminal 38 is a signal obtained by inverting the phase of the carrier color signal of the color video signal Y±C from the 1H delay circuit 33. Next, the motion detection circuit 8 will be explained with reference to FIG. Color video signal to input terminal 41
R ₁ is supplied. This color video signal R ₁ is supplied to a delay circuit 42 with a delay amount of 1H, and is delayed by 1H. Based on the color video signal from the 1H delay circuit 42, this signal is expressed as Y±C. The signal Y±C from the 1H delay circuit 42 is supplied to the next stage 1H delay circuit 43 and delayed by 1H, thereby obtaining the signal Y〓C. In the synthesizer 44, the signal R ₁ (=Y〓C) from the input terminal 41 and the signal Y〓C from the 1H delay circuit 43 are added to obtain signal 2 (Y〓C), and this Signal 2 (Y〓C) is supplied to the attenuator 45 and is attenuated by 1/2, resulting in signal Y〓
C is obtained. In the synthesizer 46, the signal Y≓C from the attenuator 45 is subtracted from the signal Y±C from the 1H delay circuit 42, and the subtraction output is supplied to the bandpass filter 47. ±
2C is obtained. In the synthesizer 48, the signal ±2C from the bandpass filter 47 is subtracted from the signal Y±C from the 1H delay circuit 42, and the signal Y〓C is obtained.
is output. The color video signal Y〓C from the synthesizer 48 is obtained by inverting the phase of the carrier color signal ±C of the color video signal Y±C from the 1H delay circuit 42. On the other hand, the signal R ₂ ' from the input terminal 49 is
The signal is supplied to a 1H delay circuit 50 and delayed by 1H. The signal from this 1H delay circuit 50 is used as the basis, and is expressed as Y〓C. And synthesizer 51
At this time, the signal Y〓C from the 1H delay circuit 50, which is delayed by one frame, is subtracted from the signal Y〓C from the synthesizer 48. The output of the synthesizer 51 is 1
The more violent the movement between different frames, the higher the output level of the synthesizer 51, and the quieter the movement, the lower the output level, so that the movement of the screen can be detected. A detection signal is supplied from this synthesizer 51 to a control circuit 52, a control signal obtained from an output terminal 53 is supplied to a synthesis circuit 9 shown in FIG. The combination ratio of each signal is controlled. Next, referring to FIG. 6, the line addition circuit 10
I will explain about it. A color video signal R ₁ is supplied to the input terminal 61 . This color video signal R ₁ is supplied to a delay circuit 62 with a delay amount of 1H, and is delayed by 1H. Based on the color video signal from the 1H delay circuit 62, this signal is expressed as Y±C. The signal Y±C from the 1H delay circuit 62 is supplied to the 1H delay circuit 63 at the next stage and delayed by 1H, thereby obtaining the signal Y〓C. In the synthesizer 64,
Signal R ₁ (=Y〓C) from input terminal 61 and 1H
The signal Y〓C from the delay circuit 63 is added to obtain the signal 2 (Y〓C), and this signal 2 (Y〓C) is supplied to the attenuator 65 and attenuated by 1/2 to become the signal Y
〓C is obtained. In the synthesizer 66, the signal Y≓C from the attenuator 65 is subtracted from the signal Y±C from the 1H delay circuit 62, and the subtraction output is supplied to the bandpass filter 67. ±
2C is obtained. The signal ±2C from the bandpass filter 67 is supplied to an attenuator 68 where it is drastically attenuated to 1/2. In the synthesizer 69, the 1H delay circuit 62
from the signal Y±C from the attenuator 68 to the signal ±C from the attenuator 68
is subtracted, and a signal, ie, a luminance signal Y, is output. The signal Y is supplied to a 1H delay circuit 70 and delayed by 1H. In the combiner 71, the signal Y from the combiner 69 and the signal Y from the 1H delay circuit 70 are added, and the output 2Y is supplied to the attenuator 72, where its level is halved and the signal Y is obtained.
On the other hand, the signal ±C from the attenuator 68 is switched by the changeover switch 73, and one is supplied as is and the other is supplied to the synthesizer 76 via the phase inversion circuit 75, where it is added to the luminance signal from the attenuator 72. A color video signal Y±C obtained by line addition of the luminance signals is obtained from the output terminal 77. The changeover switch 73 is controlled by a control signal from the output terminal 74, that is, from the control circuit 17. In each circuit of Figures 3 to 6, signal processing is performed based on a signal delayed by 1H, so the first
In the figure, the signal _R1 directly supplied to the switching circuit 11 is also delayed by 1H using a 1H delay circuit (not shown). The common parts of this 1H delay circuit and the circuits shown in FIGS. 3 to 6 can be shared. Next, the operation of the processing circuit of the above-described embodiment will be explained using the following table.

【table】

Claims (1)

[Claims] 1. A first comparison circuit that compares the field sequentiality of the input decoded video signal and the field sequentiality of the reference signal, and the phase of the carrier color signal of the input decoded video signal and the phase of the carrier color signal of the reference signal. a second comparison circuit that receives the input decoded video signal and outputs first and second decoded video signals having a time difference of one frame from each other through delay processing; The first and second decoded video signals are supplied from the means, and the first and second decoded video signals are supplied from the motion detection circuit that detects the magnitude of movement of the video signal and the delay means. , a first phase inversion circuit that inverts the phase of the carrier color signal of the first decoded video signal using the frame correlation of the video signal and outputs the inverted signal;
a second phase inversion circuit which is supplied with the decoded video signal and inverts the phase of the carrier color signal of the first decoded video signal using the line correlation of the video signal and outputs the inverted phase; a synthesis circuit for synthesizing the output video signal of the phase inversion circuit and the output video signal of the second phase inversion circuit at a ratio according to the detection result of the motion detection circuit;
a switching circuit which is supplied with the decoded video signal of and the output video signal of the synthesis circuit and selectively outputs these signals, and based on the comparison results of the first comparison circuit and the second comparison circuit. a control circuit for controlling the delay means and the switching circuit; The output timing of the input decoded video signal is controlled by the control circuit so as to be shifted by one field from when they match, and the switching circuit is configured to control the phase of the carrier color signal of the input decoded video signal. outputting the first decoded video signal supplied from the delay means when the phase of the carrier color signal of the reference signal and the carrier color signal of the reference signal match;
The control circuit controls to output the decoded video signal supplied from the synthesis circuit when the phase of the carrier color signal of the input video signal and the phase of the carrier color signal of the reference signal do not match. A color video signal processing circuit characterized in that: