JPH0474746B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method for transferring a specific storage area within a storage means to another storage area.

[Prior Art] Conventionally, in an information processing device or the like, when transferring a rectangular area 2 from SADD in a storage area in a storage device 1 as shown in FIG. 1 to a rectangular area 3 from DADD, for example, The transfer control shown below was performed.

FIG. 2 is a block diagram of an information processing device having a data transfer function, in which 1 is a storage device, 10 is a transfer control unit that controls addresses and read/write data with the storage device 1 during data transfer;
1 is a data control unit that controls data within the transfer control unit, and 12 is an address control unit that also controls addresses within the transfer control unit 10. 13 is a central processing unit, and 14 is an input/output device.

Details of the data control section 11 are shown in FIG.

In the figure, 20 is an S register that stores read data from the rectangular area 2, 25 is a shift unit that shifts the contents of the S register 20 according to the value of the SH register 26, and 26 is a rectangular area 3 to which the value of the S register 20 is transferred. Shift part 2 for adjusting to the bit position of
27 is a function register in which logical operations (AND, OR, exclusive OR, etc.) instructions are stored in the function unit 30; 28 is a mask register; 29
D stores read data from rectangular area 3
Register, 30 is S register 20 and D register 2
A function section 31 performs a logical operation on the value from 9 in accordance with the instruction indicated by the above-mentioned function register; This is a selector that masks and outputs the data to be written into the rectangular area 3. In order to perform data transfer in bit units, unnecessary bits of the data read in bytes (or words) from storage device 1 are masked and deleted, and the data before rewriting is This is to make it valid.

Next, a detailed block diagram of the address control section 12 is shown in FIG.

In the figure, 40 is an S selector, 41 is an S address register indicating the read start address for each row of the rectangular area 2, and 42 is a memory access address of the rectangular area 2 of the storage device 1 based on the value of the S address register 41. S address counter shown, 43 is an adder, 4
4 is an X register indicating the horizontal length X of the rectangular area;
45 is an X counter that detects the end of data transfer of horizontal length X, and 46 is vertical length Y of the rectangular area.
47 is a Y counter that detects the end of vertical length Y data transfer, that is, the end of all data transfer; 48 is a timing circuit that controls the read timing of the storage device 1; 49 and 54 are 1 of the storage device 1; SP register and DP register indicating the length of a line; 50 a D selector; 51 a D address register indicating the read start address for each line of the rectangular area 3; 52 a D address counter indicating the memory access address of the rectangular area 3; 53 is a D adder.

With the above configuration, the memory space shown in Figure 1 is
When moving rectangular area 2 of X bits horizontally and Y bits vertically from address SADD to rectangular area 3 of X bits horizontally and Y bits vertically from address DADD, [SADD] is moved from the central processing unit 13 or the like via the S selector 40. and set it in the S address register 41, and
Store the number of bits
Store the length P of one row of the storage device 1 in the register and DP register, and if data needs to be shifted, store the number of shifts in the SH register,
Instruct data transfer.

As a result, the transfer control unit 10 transfers the value of the S address register 41 to the S address counter 42, the value of the X register 44 to the X counter 45, and the value of the Y register 4
The value of 6 is set to the Y counter 47, and the value of the D address register 51 is set to the D address counter 52.

First, the data in the rectangular area 2 indicated by the address indicated by the S address counter 42 (hereinafter referred to as S-DATA) is read out, and the data in the S register 2 is read out.
Store at 0. Also, the contents of the address indicated by the D address counter 52 in the rectangular area 3 (hereinafter D-
DATA) is stored in the D register.

The data control unit 11 transfers S-DATA stored in the S register 20 to the SH register 26 as necessary.
The shift unit 25 shifts by the amount specified in ,
This shifted value and D− stored in the D register
DATA is logically operated in the function section according to the specification of the function register 27, and the logically operated data (SD-DATA) and D-DATA are selected by the mask register 28, and sent to the rectangular area 3 by the selector 31. The data is output as write data and written to the address specified by the D address counter 52. Masking by the mask register 28 and shifting by the shift unit 25 are performed when the first and last bit positions of each row in the rectangular area 3 do not match the byte or word boundary of the start bit position of the data transferred from the rectangular area 2. This is to make a part of the read D-DATA valid as is. A conceptual diagram in this case is shown in FIG. In this way, the difference in bit position between S-DATA and D-DATA is corrected.

As described above, the contents of the address indicated by the S address counter 42 are logically operated to the address indicated by the D address counter 52, bit alignment is performed, and the data is transferred. Therefore, the timing circuit 48
As a result, the S address counter 42 is counted up, and the X counter is also counted down by a predetermined number. At the same time, the timing circuit 48 counts up the D address counter 52. Then, the contents of the addresses indicated by the S address counter 42 and the D address counter 52 are transferred.

Data is transferred sequentially, and when the transfer of one horizontal line is completed, the X counter 45 becomes 0. With this [X counter] = 0, the value obtained by adding the value of the SP register 49 to the value of the S address register 41 by the S adder is added to the S address register 4 via the S selector 40.
At the same time, the Y counter 47 is counted down by one. Through this process, the start address of the rectangular area 2 of the next row is set in the S address register 41. And this S address register 4
Set the value of 1 in the S address counter 42, and
The value of the X register 44 is set in the counter 45 again. Similarly, D address register 51 and DP
The value of the register 54 is added by the D adder 53 and sent to the D address register 51 via the D selector 50.
and sets the value of the D address register 51 to the D address counter 52.

In this way, data transfer for the next row is started.

The above process is repeated, and when the value of the Y counter 47 becomes "0", the transfer of the rectangular area is completed.

[Problems to be Solved by the Invention] Conventionally, only the data transfer as described above was performed, and the contents of the rectangular area 2 were left as they were. For this reason, for example, if the storage device 1 is a display memory such as a display device, when moving the display corresponding to rectangular area 2 to rectangular area 3, the data in rectangular area 2 must be erased again after data transfer. However, the processing is complicated and the processing time is long.

[Means for Solving the Problems] The present invention has been made in view of the drawbacks of the above-mentioned conventional examples, and it transfers storage information in a specific storage area of a storage means to another storage area, and also transfers storage information in a specific storage area of a storage means. The purpose of the present invention is to propose a data transfer method that allows an area to be rewritten with arbitrary data, and that allows data transfer and rewriting of the data transfer source storage area at the same time.

The present invention includes the following configuration as one means for solving the above-mentioned problems.

That is, a storage means having a plurality of storage locations for storing information and storing a plurality of bits of information in each storage location, and a first storage means that generates address information specifying the plurality of storage locations of the storage means. addressing means; second addressing means for generating address information specifying the plurality of storage locations of the storage means; and address means for generating address information specifying the plurality of storage locations of the storage means; another storage means for storing arbitrary information to be written into one; a first control means for reading information from one storage location of the storage means based on address information of the first address means; and a first address. When masking and writing the arbitrary information in another storage means based on the address information of the first address means, part of the storage information of the other storage means is written in one storage location of the storage means based on the address information of the first address means. and a third control means for writing the information read by the first control means into the storage means based on the address of the second address means.

[Operation] In the above configuration, when moving a figure or the like on the storage device, it becomes possible to mask and write any separately stored arbitrary information at an appropriate time. Therefore, even if any information is transferred, the transfer source area can be filled with optimal information that matches the background.

[Example] An example of the present invention will be described below with reference to the drawings.

FIG. 6 is a diagram showing details of the data control section 11 of the transfer control section 10 shown in FIG. 2 according to an embodiment of the present invention, and the same parts as in FIG. 3 are given the same numbers.

In this embodiment, in addition to the registers shown in FIG. 3, a C register 21 is added, and arbitrary data is set in this C register 21. Then, between the shift section 25 and the function section 30, the output data from the shift section 25 and the above-mentioned C register 2 are connected.
SEL1, which is a selector that switches and outputs the output data from function register 27 using SEL signal 32, is added to function register 27 and function section 30. 3
An F selector 23 is added that selects and outputs a logic operation instruction instruction of 0 and a logic operation inhibition instruction.

This reads the contents of the [S address counter] address in rectangular area 2, performs a shift logical operation on it, performs mask processing, stores it in the [D address counter] address in rectangular area 3, turns off the SEL signal, and stores it in the C register 21. This is to control the rectangular area 2 so that the data of the C register 21 is written after data transfer by storing the contents of the C register 21 to the address [S address counter] only by masking.

The configuration of the address control section 12 is the same as that in FIG. 4.

The data transfer process of the apparatus of this embodiment will be explained in detail below with reference to the flowchart of FIG.

First, in step 101, predetermined setting values are set in each register. This transfers "SADD" to the S address register 41 via the S selector 40, "DADD" to the D address register 51 via the D selector 50, and the horizontal length "X" of the rectangular area to be transferred to the X register 44. The vertical length "Y" of the rectangular area to be transferred to the Y register 46, the number of cysts in the shift section 25 to the SH register 26, the instruction specifying the logical operation in the function section 30 to the function register 27, and the mask register 28 The mask data in selector 31 is transferred to SP register 4.
9 and the DP register 54 are set to a number equivalent to the horizontal length of the storage area of the storage device 1, and furthermore, the C register 21 is set to the data to be written to the rectangular area 2 after data transfer.

Next, in step 102, the value of the Y register 46 is changed to Y.
The remaining S address register 41 is set to the S address counter 42, the D address register 51 is set to the D address counter 52, and the X register 44 is set to the X counter 45 at step 103. Then, in step 104, the contents of the address (S address counter) in the rectangular area 2 of the storage device 1 are read out and set in the S register 20. At the same time, to the function section 30
The SEL signal 32 is turned on so that the data from the shift section 25 is outputted via SEL1 (22).

At step 105, the data from the S register 20 is shifted by the shift section 25 by the number specified by the SH register 26. This shifted output data from the shift unit 25 is input to SEL1 (22),
Since the SEL signal 32 is on, data from this shift section 25 is selectively outputted from SEL1 (22).
The SEL signal 32 is also input to the F selector 23, and the logic operation command from the function register 27 is input to the function section 30. Next, in step 106 (D address counter)
The contents of the rectangular area 3 of the storage device 1 specified by the address are read into the D register 29. Then, in step 107, the data from the shift section 25 sent to the function section 30 via SEL1 (22) and the data read from the D register 29 are sent to the function section 30 via the F selector 23. A logical operation is performed according to the specification of the function register 27. This calculation result and the value of the D register 29 are input to the selector 31. The mask data set in the mask register 28 is also input to the selector 31 at the same time, and in step 108, the input data to the selector 31 is masked according to this mask data, and the masked data is output to the data bus 16. This masking data is in a data format that should be transferred to rectangular area 3, and this value is
109, the data is written to the address indicated by the D address counter 52. Then, in step 110, the SEL signal 32 is turned off.

As a result, C register 21 is more important than SEL1 (22).
The value of is selected and outputted, and the logical operation prohibition instruction is selected and outputted from the F selector 23 and the function register 27. For this step 111
As shown in the figure, the value of the C register 21 is input to the function unit 30 via SEL1 (22), and the function unit 30 outputs it as is without performing any logical operation, and the value of the C register is input as is to the selector 31. become.

Then, in step 112, as in step 108, masking is performed according to the mask data in the mask register 28 and output to the data bus 16. This data is written to the address indicated by the S address counter 42 in step 113. Then, in step 114, the value of the X counter 45 is counted down by the number n of transfer end bits.

When the above processing is completed, the data transfer for n bits to rectangular area 3 is completed, and the value of the C register is written to rectangular area 2, and the data transfer for one line is completed in step 115. , check whether the X counter 45 has reached "0". If the X counter 45 is “0”, step 118 will be described later.
If it is not "0", the S address counter 42 is incremented by one in step 116, and then the D address counter 52 is incremented by one in step 117, and the process returns to step 104.

When the value of the X counter 45 is determined to be "0" in step 115 and the transfer of data for the horizontal length X is completed, the process proceeds to step 118, where the Y counter 47 is set to 1.
countdown. Then, in step 119, it is checked whether the Y counter 47 is "0" or not. If the Y counter 47 is "0", it means that all data transfer has been completed, and the data transfer process is ended.

If the data transfer has not been completed, the Y counter 47 is a positive value, and the process proceeds to step 120, where the data transfer is completed.
The values of the address register 51 and DP register 54 are added by the D adder 53, and the values of the address register 51 and DP register 54 are added again.
Set to 1. As a result, the start address of the next row of the rectangular area 3 is set in the D address register 51. Then go to step 121 and
Similarly to 120, the values of the SP register 49 and the S address register 41 are added by the S adder 43, and the start address of the rectangular area 2 is set in the S address register 41. Then, the process returns to step 103 to continue data transfer.

As explained above, in this embodiment, the C register 21
By setting arbitrary data in the C register 21, it is possible to store the data in the C register 21 in the transfer source storage area and to transfer the data at the same time. When using the ``0'' code in a numeric data storage memory, data transfer and clearing of the transfer source memory area can be performed simply by setting the ``0'' code.

Further, by making the C register 21 have a buffer structure capable of storing a plurality of pieces of data, a specific pattern over the entire rectangular area 2 can be specified and stored.

[Effects] As explained above, according to the present invention, it is possible to provide a data transfer method that transfers storage information in a specific area of a storage means to another storage area and rewrites the specific area of the transfer source with arbitrary information. Processes that were conventionally divided into two and executed individually can now be executed as one operation while sharing one address, reducing processing time and simplifying control.

Furthermore, when moving figures etc. on a storage device, it is possible to mask and write arbitrary information at the appropriate time, and even if all kinds of information are transferred, the transfer source area can be optimally adjusted to match the background. It can be filled with information.

[Brief explanation of the drawing]

Fig. 1 is a diagram schematically representing the data transfer area of a storage device, Fig. 2 is a block diagram of an information processing device capable of data transfer, and Fig. 3 is a block diagram of a data control unit in conventional data transfer control. , FIG. 4 is a block diagram of the address control section in the data transfer control section, FIG. 5 is a diagram showing an example of correcting the difference in bit position in data transfer, and FIG. 6 is a diagram showing data transfer control of an apparatus according to one embodiment of the present invention. FIG. 7 is a block diagram of the data control unit in FIG. In the figure, 1...storage device, 10...transfer control unit, 11
...Data control section, 12...Address control section, 13...
Central processing unit, 14...I/O device, 20...S register, 21...C register, 22...SEL1, 23...
F selector, 25... Shift section, 26... SH register, 27... Function register, 28... Mask register, 29... D register, 30... Function section, 31... Selector, 40... S selector,
41...S address register, 42...S address counter, 43...S adder, 44...X register, 4
5...X counter, 46...Y register, 47...Y counter, 48...timing circuit, 49...SP register, 50...D selector, 51...D address register, 52...D address counter, 53...D adder, 54... DP register, 60...SEL, 62...holding register.

Claims (1)

[Scope of Claims] 1. Storage means having a plurality of storage locations for storing information and storing a plurality of bits of information in each storage location, and a transfer for specifying the plurality of storage locations of the storage means. a first address means for generating source address information; a second address means for generating forwarding address information specifying the plurality of storage locations of the storage means; based on the address of the first address means; one of the plurality of storage locations of the storage means read out;
another storage means for storing arbitrary information to be written in the first address means; a first control means for reading information from one storage location of the storage means based on address information of the first address means; a second control means for masking and writing some bits of the storage information of the other storage means into one storage location of the storage means based on the address information of the address means of the first control means; and third control means for writing the issued information into the storage means based on the address of the second address means.