JPH0510695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address translation device in an information processing device, and more particularly to an address translation device using an address translation buffer.

(Prior Art) Conventionally, in a processing device that performs address translation, TLB (Translator) is used as shown in FIG.
tion Lookaside Buffer)
1 is used for address translation. That is, the logic section L1 of the address register 22 accesses the entry direction of the buffer 21 (TLB), and the obtained real address is transferred to the address register 22.
The comparator 23 compares the logic part L2 with the comparator 23 to detect whether it is a hit or a miss.If there is a miss, the address translation table inside the main memory is loaded into this entry, and then the address translation is performed. method is generally adopted.

(Problems to be Solved by the Invention) In the above-mentioned conventional TLB system, each entry has a valid bit that indicates whether address translation data is valid or invalid. The path that compares the logical parts of addresses and detects hits/misses becomes a link in delay time and is therefore a major factor in determining machine cycles. In addition, each time a mishit occurs, only the necessary entries in the address translation buffer are loaded, so when there are many mishits, loading from memory to the buffer is performed frequently, which greatly increases the processing speed of the entire device. The disadvantage was that it decreased.

An object of the present invention is to provide an address translation buffer in which each logical address space is divided into a plurality of subspaces having the same number of pages, and which holds a copy of an address translation table for the entire logical address space in order to perform address translation at high speed. Further, the address translation buffer is provided with an indicator indicating the validity of the copy of the address translation table for each division unit divided into a plurality of subspace units, and the indicator allows reference to the address translation buffer and It is an object of the present invention to provide an address translation device that eliminates the above-mentioned drawbacks by controlling the load for each division unit, and is configured so that the processing speed does not decrease.

(Means for Solving the Problems) An address translation device according to the present invention includes an address translation buffer and control means.

The address translation buffer is divided into a plurality of subspaces having the same number of pages as the logical address space divided into pages of the same capacity, and holds a copy of the address translation table for the entire logical address space. It has an indicator indicating the validity of the copy of the table and is used to perform address conversion at high speed.

The control means is for controlling reference/load to the address translation buffer for each division unit by the indicator.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an address translation device according to the present invention. In Figure 1, 1
is the first register, 2 is the address translation buffer,
3 is the main memory, 4 is the second register, and 5 is the first register.
6 is a load control circuit, 7 is a second selector, and 8 is a third register.

In FIG. 1, among the logical addresses input to the first register 1, the space number S is the signal line 10.
1 to the first selector 5 and second selector 7, the page number P is sent to the address conversion buffer 2 via the signal line 102, and the intra-page address D is sent to the third register 8 via the signal line 103. be done. Main storage device 3 to signal line 10
4, the load data is transferred to address conversion buffer 2.
An entry is selected from each buffer 2-0 to 2-7 of the address conversion buffer 2 according to the page number sent out through the signal line 102, and sent out to the second selector 7 through the signal line 105. The second selector 7 converts one of the real parts R of the addresses sent from the address conversion buffers 2-0 to 2-7 into the information S on the signal line 101.
and sends it to the R section of the third register 8 from the signal line 106. Second register 4-0~
This is an 8-bit register consisting of 4-7, which is used to temporarily store an indicator indicating the validity of the copy of the address translation table held in the address translation buffer 2, and 4-0 to 4-7 are , respectively correspond to address translation buffers 2-0 to 2-7, and valid address translation data is stored in address translation buffer 2.
When the second
"1" is set in the bit positions corresponding to registers 4-0 to 4-7. The output of the register 4 is output to the first selector 5 via the signal line 107,
The first selector 5 selects the second registers 4-0 to 4.
-1 bit from the output of signal line 101
and outputs it to the load control circuit 6 as a hit/miss signal. The load control circuit 6 suppresses the request when a mishit occurs, instructs the load of address translation data to the division unit of the address translation buffer 2 where the mishit has occurred, and sets "1" in the corresponding division unit of the corresponding second register 4. do.

With the above configuration, the present invention will be explained in more detail. To simplify the explanation in FIG. 1, space number 5 is 5 bits, page number P is 9 bits, and the number of entries in address translation buffer 2 is 512.
x8=4096 entries, the real part R of the address is 9 bits, and the intra-page address D is 12 bits.

Now, when a logical address with S=4, P=146, and D=2748 is input to register 1, the real parts R0 to R0 of the address corresponding to P=146 are input from address conversion buffers 2-0 to 2-7. R7 is read.
R4 corresponding to S=4 is selected by the second selector 7 and set in the R section of the third register 8. By the way, address D=2748 on the page is,
It is directly input into the third register 8. Therefore, if R4=239, from the third register 8
662392748" is output as the real address. If the content of second register 4 is 10101111, the content of register 4-4 is "1", so
"1" is selected by the first selector 5 and reported to the load control circuit 6 as a hit signal, indicating that the real address is valid.

Next, assuming that the logical address S=3, P=146, D=2748 is input to the first register 1, the real address “4952748” is output from the third register 8. . At this time, the contents of the register 4-3 are 0, so the first selector 5
"0" is output to the load control circuit 6 as a miss signal.

At this time, the load control circuit 6 suppresses the request for the above-mentioned real address, generates the first address of the address translation table inside the main storage device 3 for the address translation buffer 2-3, and saves all entries of the address translation buffer 2-3. Instructs to load address translation data all at once. When the loading of the address translation data is completed, "1" is written in the second register 4-3, indicating that the address translation buffer 2-3 has become valid, and the request suppression is released.

The above is a series of operations, and in the present invention, the human/
Mishit detection is performed by selecting the output of the second register 4 with the first selector 5. Therefore,
Unlike conventional TLBs, there is no path for reading and detecting valid bits from the address translation buffer, and this does not become a bottleneck in machine time. Further, in the event of a mishit, address translation data is loaded into all entries in the divided unit of the address translation buffer including the entry where the mishit has occurred, so that it is difficult for misses to occur continuously after loading.

(Effects of the Invention) As explained above, the present invention provides an address translation buffer for the entire logical space, and also provides an independent display indicating the validity of the address translation buffer divided into equal capacities. Since hits/misses can be detected without creating a bottleneck in the cycle, the machine cycle can be improved. Additionally, when a mishit occurs, address translation data can be loaded into all address translation buffers in the corresponding subspace, making it difficult for consecutive misses to occur, resulting in a significant improvement in processing speed. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an address translation device according to the present invention. FIG. 2 is a block diagram for explaining address translation according to the prior art. 1, 4, 4-0 to 4-7, 8...Register, 2,
2-0 to 2-7...Address conversion buffer, 3...Main storage device, 5, 7...Selector, 6...Load control circuit, 101 to 110...Signal line.

Claims (1)

[Scope of Claims] 1. Each logical address space divided into pages of the same capacity is divided into a plurality of subspaces having the same number of pages, and holds a copy of the address translation table for the entire logical address space, and an address translation buffer for performing address translation having an indicator indicating the validity of a copy of an address translation table; and controlling references/loads to the address translation buffer for each division unit by the indicator; 1. An address translation device comprising: control means.