JPH0654477B2 - Storage device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device including an address translation buffer and a cache memory.

2. Description of the Related Art FIG. 3 shows a block diagram of a conventional storage device. In the figure, the page number portion of the logical address is converted into a physical address by the address conversion buffer 101. here,
The case of a direct map type address conversion buffer will be described. The address translation pair 102a, 102b is read using the lower bits of the page number. The logical address 102a is compared with the upper bits of the page number by the comparator 103, and if they match, the physical address 102b is considered to be valid. The cache memory 105 is accessed by the page offset of the logical address. In this example, the size of the cache memory 105 is the same as the page size. A physical address is stored in the tag unit 106 of the cache memory 105, and this physical address and the physical address 102b of the address translation pair are compared by the validity detector 107, and if they match, the data unit 107 of the cache memory 105.
The data read from is considered valid.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a conventional circuit, the bit width of the physical address stored in the tag portion of the cache memory is wide, and therefore,
The circuit scale of the entire tag part is large, the reading speed is slow,
Further, there is a problem that the effectiveness detection is slow. The present invention has been made in view of the above points, and an object of the present invention is to provide a storage device capable of reducing the circuit scale of the tag unit and reading the tag unit and detecting the effectiveness at high speed.

Means for Solving the Problems In order to solve the above problems, the present invention stores the number of an address translation pair in a tag section of a cache memory, and a validity detector reads the value of the read tag section and the address translation. The number of the address translation pair used for is compared to determine the validity of the data read from the cache memory.

Effect The present invention has the above-described configuration, which reduces the bit width of the tag portion of the cache memory and the bit width of the input of the validity detector, and can speed up the reading of the tag portion and the validity determination.

Embodiment (Embodiment 1) FIG. 1 is a block diagram showing an embodiment of a storage device of the present invention. In FIG. 1, 1 is a direct mapping type address conversion buffer, 2a and 2b are address conversion pairs, 2a stores a logical address, and 2b stores a physical address. The logical address 20 is composed of a page number and a page offset, and the lower part of the page number is used as an address translation pair number to read the address translation pair. Reference numeral 3 is a comparator, which compares the read logical address 2a with the higher order page number, and if they match, the address conversion pair
It can be seen that 2a and 2b are effective. Reference numeral 6 is a cache memory, which includes a tag unit 7 and a data unit 8. In this example, the size of the cache memory 6 is one page, so all bits of the page offset of the logical address are used at the time of access. For each entry in the tag section 7,
The address translation pair number 9 and a valid bit 12 indicating the validity of the entry are stored. A validity detector 10 compares the address translation pair number 4 with the address translation pair number 9 of the tag unit 7, and the data read from the cache memory 6 from the valid bit 12 and the result of the comparator 3. Determine the effectiveness of. When the address translation pair is valid and the data in the cache memory 6 is not valid, the external memory is accessed even by using the physical address 26 read from the address translation buffer 1. Also, address translation pairs
When 2a and 2b are replaced by a new address translation pair,
The invalidation request signal 11 is supplied to invalidate all the entries in the cache memory 6 having the address translation pair numbers to be replaced. As a result, even when the address translation pair is replaced, the correspondence between the address translation pair and the data in the cache memory can always be maintained correctly. For example, if the logical address is 32 bits and the number of address translation pairs is 32, the number of the address translation pair can be represented by 5 bits, and the bit width of the tag unit 7 of the present invention is 6 including the valid bits 12. Is a bit. If the size of one page is 4 Kbytes, the page offset is 12 bits, the page number is 20 bits, and the bit width of the conventional tag part is 21 bits when the effective bits are combined.

(Embodiment 2) FIG. 2 shows a block diagram of another embodiment of the present invention. In FIG. 2, reference numeral 1 denotes a full associative address translation buffer, which searches by the page number of the logical address 20 and outputs the corresponding address translation pair selection signal 40 when the address translation pairs 2a and 2b having the same value exist. To be done. On the other hand, in this example, the size of the cache memory 6 is smaller than one page, and the cache memory 6 is accessed using part of the page offset of the logical address 20. A portion of the page offset that is not used for access is stored in 35, and an address translation pair number is stored in 34. 33 is a valid bit and indicates whether or not the entry is valid. The validity of the data read from the cache memory 6 is determined by the two validity detectors 31 and 32. The address translation pair number 34 of the tag portion 7 is the validity detector 31.
Is applied to the address translation pair selection signal 40, and if a match is found, a match signal 36 is provided to the validity detector 32. The validity detector 32 compares the logical address 20 with a part of the page offset stored in the tag unit 7, and determines the validity of the data in the cache memory 6 from the match signal 36 and the validity bit 33. Here, for example, assuming that the logical address is 32 bits, the page size is 4 Kbytes, the cache size is 1 Kbyte, and the address conversion pairs are 32, the bit width of the tag portion in the present invention is 8 bits including valid bits,
In the conventional example, it is 23 bits. Further, according to the present invention, the determination of the validity of the cache memory does not require the reading of the physical address portion 26 of the address translation pair, so that the determination can be performed at high speed. When the address translation pair is replaced, all the data having the address translation pair number replaced by the invalidation request signal 11 is invalidated as in the first embodiment.

EFFECTS OF THE INVENTION As described above, according to the present invention, the tag portion of the cache memory is small, and the validity of data can be determined at high speed, which is extremely useful in practice.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a storage device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a storage device according to another embodiment of the present invention, and FIG. It is a block diagram which shows a memory | storage device. 1 ... Address translation buffer, 2a, 2b ... Address translation pair, 6 ... Cache memory, 7 ... Tag section, 8 ... Data section, 10,31,32 ... Validity detector, 11 ... Invalid Request signal.

Claims (3)

[Claims] 1. An address translation buffer, a cache memory, and a validity detector, wherein the address translation buffer has a plurality of address translation pairs for translating a logical address into a physical address, and the cache memory has a tag unit. And a data section, the tag section stores the number of the address translation pair, and the validity detector reads the number of the address translation pair used for the address translation and the tag section of the cache memory. A storage device for detecting the validity of data in the cache memory by comparing the numbers of address translation pairs. 2. The tag unit of the cache memory stores the number of the address translation pair and a part of the logical address, and the validity detector includes the number of the address translation pair used for the address translation and a part of the logical address. 2. The storage device according to claim 1, wherein the validity of the cache memory is detected by comparing the contents of the tag portion of the cache memory. 3. The storage device according to claim 1 or 2, wherein the cache memory invalidates the data having the designated address translation pair number in response to the invalidation request signal.