JPH0519157B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a liquid crystal panel drive circuit having a sample and hold circuit.

BACKGROUND ART In recent years, liquid image display devices using liquid crystal panels have been attracting attention, and various liquid crystal panel drive circuits have been proposed.

An example of the conventional liquid crystal panel drive circuit mentioned above will be described below with reference to the drawings.

FIG. 4 shows the configuration of an example of a conventional liquid crystal panel drive circuit, and FIG. 5 shows its timing chart.

In Fig. 4, 1 is a video input terminal, 2, 3,
4, 5, and 6 are control signals Q _o , G ₁ , G ₂ ,
a switching element controlled by G ₁ and G ₂ ;
C _oa and C _ob are sample and hold capacitors, 7 is a buffer amplifier, and 8 is a video output terminal.

The video input terminal 2 constitutes a sampling switch, and the video input terminals 3 and 5 and switching element _Coa constitute a first hold circuit, and the video input terminal 4.6 and switching element _Cob constitute a second hold circuit. It constitutes a circuit.

The operation of the conventional liquid crystal panel drive circuit configured as described above will be explained based on the timing chart shown in FIG.

V _io is the waveform of the input signal applied to the video input terminal 1, and one horizontal period is expressed as 1H (hereinafter, one horizontal period is abbreviated as 1H). G ₁ and G ₂ are control pulses for the sample and hold circuit, and both G ₁ and G ₂ have a period of two horizontal periods, and their phases are shifted from each other by π. Also, the falling of G ₁ and the rising of G ₂ ,
The rising edge of G ₁ and the falling edge of G ₂ coincide in timing. Q _o is the n-th sampling pulse when the 1H video signal is time-divided, and is used to sample the information of the video signal supplied to the nth column of the liquid crystal panel. V _oa and V _ob are the voltages applied to the sample and hold capacitors Coa and C _{ob ,} respectively, and V _put is the waveform of the output signal from the video output terminal 8. The video output terminal 8 is connected to the nth column electrode (not shown) of the liquid crystal panel.

In the timing chart, since G ₁ is on and G ₂ is off during the period t ₁ , the information on the sample and hold capacitor C _ob is transmitted to the video output terminal 8, and the information on the sample and hold capacitor C _oa is transmitted to the video output terminal 8.
The video signal information is sampled by the sampling pulse _Qo . Next, during the period _t2 , _G1 is off and _G2 is on, so the information of _Coa sampled during the period _t1 is transmitted to the video output terminal 8, and the sampling pulse of _Qo is sent to _Cob . The video signal information is sampled by.

In the following periods t ₃ , t _{4 .} . . , the same operations as in the periods t ₁ and t ₂ are repeated, respectively.

Problems to be Solved by the Invention However, in such a conventional circuit, in the sample and hold control pulses G ₁ and G ₂ , the falling of G ₁ and the rising of G ₂ , and the rising of G ₁ and the falling of G ₂ While the timings of switches 3, 4, and 4, which are performing sample and hold operation,
Since the transient switching time of the elements composing 5 and 6 (such as MOS analog switches) is not zero, when G ₁ and G ₂ switch, G ₁ ,
There is a period when both _G2 are on,
Crosstalk occurs between V _oa and V _ob , and accurate video signal information is not transmitted to the video output terminal 8.
There was a problem.

In view of the above problems, the present invention has no crosstalk between the two sample and hold voltages V _oa and V _ob , and
It is an object of the present invention to provide a liquid crystal panel drive circuit that transmits accurate video signal information to a video output terminal 8.

Means for Solving the Problems In order to solve the above problems, the liquid crystal panel drive circuit of the present invention includes a sampling switch that time-divisionally samples the video signal of one horizontal scanning period, and a sampling switch whose phases are approximately 180 degrees from each other. A first hold consisting of two series-connected hold operation control switches that are opened and closed by control pulses of two different horizontal scanning periods, and a sample-and-hold capacitor inserted between the connection point of these switches and ground. The circuit has the same configuration as this first hold circuit,
It consists of a second hold circuit in which the phase of the control pulse of two horizontal scanning periods applied to the hold operation control switch is opposite to that of the first hold circuit, and the first hold circuit and the second hold circuit are connected to each other. They are connected in parallel, and their input ends are connected in series to the sampling switch, so that the phases applied to the hold operation control switch are approximately equal to each other.
The control pulses have two horizontal scanning periods that differ by 180 degrees, and the period during which they are both off is longer than the transient switching time of the elements constituting the first and second hold circuits.

Effects According to the present invention, with the above-described configuration, when the two sample-hold control pulses are switched, both pulses are turned off for a certain finite period, and then one of them is turned on. No crosstalk occurs between voltages,
Accurate video signal information can be transmitted to the video output terminal.

Embodiment A liquid crystal panel drive circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure shows the timing chart. The configuration itself is the same as that shown in FIG. That is, in Fig. 1, 1 is a video input terminal, 2, 3, 4, 5, 6
are switching elements controlled by control signals Q _o , G ₁ , G ₂ , G ₁ , G ₂ , C _oa and C _ob are sample-and-hold capacitors, 7 is a buffer amplifier, and 8 is a video output terminal.

The video input terminal 2 constitutes a sampling switch, the video input terminals 3 and 5 and the switching element _Coa constitute a first hold circuit, and the video input terminals 4 and 6 and the switching element _Cob constitute a second hold circuit.
Configure a hold circuit.

The operation of the liquid crystal panel drive circuit configured as described above will be explained below based on the timing chart of FIG.

V _io is the waveform of the input signal applied to the video input terminal 1, and one horizontal period is expressed as 1H.
G ₁ and G ₂ are control pulses for the sample and hold circuit, and both G ₁ and G ₂ have a period of two horizontal periods, and their phases are shifted from each other by π. Also, a finite value t is set between the falling edge of G ₂ and the rising edge of G ₁ , and between the falling edge of G ₁ and the rising edge of G ₂ , that is, the period during which both G ₁ and G ₂ are off. . And the value of this t is determined by the elements constituting the sample and hold circuit.
In other words, it is set longer than the transient switching time of the switching elements 3, 4, 5, and 6.

Q _o is the nth sampling pulse when the 1H video signal is time-divided, and is used to sample the information of the video signal supplied to the nth column of the liquid crystal panel. V _oa and V _ob are the voltages applied to the sample and hold capacitors C _oa and C _ob respectively,
_Vput is the waveform of the output signal from the video output terminal 8.
The video output terminal 8 is connected to an n-th column electrode (not shown) of the liquid crystal panel.

In the timing chart, since G ₁ is on and G ₂ is off during the period t ₁ , the information on the sample and hold capacitor C _ob is transmitted to the video output terminal 8, and the information on the sample and hold capacitor C _oa is transmitted to the video output terminal 8.
The video signal is sampled by a sampling pulse _Qo . Next, during period t ₂ , G ₁ is off.
Since _G2 is on, the information of _Coa sampled during the period _t1 is transmitted to the video output terminal 8, and the video signal information is sampled to _Cob by the sampling pulse of _Qo .

Hereinafter, during the periods t ₃ , t ₄ , . . . , the same operations as the periods t ₁ and t ₂ are repeated, respectively.

In this circuit, the sample and hold operation period t ₁ ,
Since there is a period t during which the sample and hold control pulses _G1 and _G2 are both off between _t2 , _t3 , _t4 , ..., the sample and hold voltages V _oa and V _ob are determined by the complete sampling period. After that, you will enter a hold period.

As described above, according to this embodiment, the period t during which the two sample-hold control pulses G ₁ and G ₂ are both off is set to be larger than the transient switching time of the elements constituting the sample-and-hold circuit. 2, which was a problem in conventional circuits.
Crosstalk between the sample and hold voltages V _oa and V _ob can be eliminated, and accurate video signal information can be transmitted to the video output terminal 8.

FIG. 3 is a specific example of the circuit configuration of the present invention,
Aluminum gate for switches 2, 3, 4, 5, 6
This is when configured with MOS analog switches. Since the transient switching period of the aluminum gate MOS is 50 _nsec to 100 _nsec , the period during which the sample and hold control pulses G ₁ and G ₂ are turned off was set to 2 to 3 _μsec .

Effects of the Invention As described above, according to the present invention, there is provided a sampling switch that samples a 1H video signal in a time-divisional manner, and a sampling switch that samples a 1H video signal in a time-division manner.
2, which is opened and closed by control pulses in the horizontal scanning period.
A first hold circuit consisting of two series-connected hold operation control switches and a sample-and-hold capacitor inserted between the connection point of the switches and ground; It consists of a second hold circuit in which the phase of the control pulse applied to the control switch for two horizontal scanning periods is opposite to that of the first hold circuit, and the first hold circuit and the second hold circuit are connected to each other.
The hold circuit is connected in parallel with the sampling switch, and its input end is connected in series with the sampling switch.
The period in which both of the horizontal scanning period control pulses are off is set to be longer than the transient switching time of the elements constituting the first and second hold circuits, which has caused problems in conventional circuits. Crosstalk between two sample and hold voltages can be eliminated, and accurate video signal information can be transmitted to the video output terminal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a liquid crystal panel drive circuit according to an embodiment of the present invention, Fig. 2 is a timing chart thereof, Fig. 3 is a circuit diagram showing a specific example of the circuit configuration, and Fig. 4 is a conventional example. The block diagram of the liquid crystal panel drive circuit shown in FIG. 5 is a timing chart thereof. 1...Video input terminal, 2, 3, 4, 5, 6...
Switching element, 7... Buffer amplifier, 8...
...Video output terminal.

Claims (1)

[Claims] 1. A sampling switch that time-divisionally samples the video signal of a horizontal scanning period, and two series-connected hold operation controls that are opened and closed by two control pulses of 2 horizontal scanning periods whose phases differ by approximately 180 degrees from each other. a first hold circuit consisting of a sample-and-hold capacitor inserted between the connection point of the switch and ground, and two horizontal The first hold circuit and the second hold circuit are connected in parallel, and the input The end of the switch is connected in series to the sampling switch, and is applied to the hold operation control switch as two horizontal scanning period control pulses whose phases differ by approximately 180 degrees from each other, and the period during which both are off is applied to the hold operation control switch. , a liquid crystal panel drive circuit characterized in that the time is longer than the transient switching time of the elements constituting the first and second hold circuits.