JPH0531827B2 - - Google Patents
Info
- Publication number
- JPH0531827B2 JPH0531827B2 JP24582486A JP24582486A JPH0531827B2 JP H0531827 B2 JPH0531827 B2 JP H0531827B2 JP 24582486 A JP24582486 A JP 24582486A JP 24582486 A JP24582486 A JP 24582486A JP H0531827 B2 JPH0531827 B2 JP H0531827B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- wiring
- board
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ひとつのパツケージ内に多数個の半
導体チツプを実装してなる、いわゆる三次元実装
マルチチツプパツケージ技術による半導体装置の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of a semiconductor device using so-called three-dimensional mounting multi-chip package technology, in which a large number of semiconductor chips are mounted in one package.
従来からこの種の半導体装置として、複数個の
半導体チツプ(LSIチツプ)を、複数枚の配線基
板にそれぞれ平面実装するとともに、これら配線
基板を順次積層方向に並設した状態で別の配線基
板上に設け、さらにこれらをひとつのパツケージ
内に実装してなる構成を有するものが知られてい
る。このような従来の三次元実装マルチチツプパ
ツケージを第3図a,b,cを用いて簡単に説明
すると、図中1はPN接合からなる能動素子およ
びその接続用配線を有し能動、受動機能を備えて
なるSi等による多数個の半導体チツプで、これら
半導体チツプ1はそれぞれがたとえば大容量メモ
リ、マイクロプロセツサの大規模論理回路等の一
定規模の機能を有し、かつこれら多数個の半導体
チツプ1全部でこの半導体装置全体の機能が構成
される。2はこれら多数個の半導体チツプ1が複
数個づつ配置固定されその機能を相互に接続する
複数枚の第1配線基板、3はこれらの第1配線基
板が立設状態で並設されることでその機能を相互
に接続する第2配線基板で、これら第1および第
2配線基板2,3は前記多数個の半導体チツプ1
と共に絶縁基板4上に載置されることでパツケー
ジ化されている。ここで、図中5aは前記各半導
体チツプ1上に形成されこれを第1配線基板2側
に電気的、機械的に接続するためのPb・Sn合金
による電極(以下バンプという)、5bは第1配
線基板2を第2配線基板側に電気的および機械的
に接続するPb・Sn合金による電極(バンプ)で、
また6は第2配線基板3と絶縁基板4を電気的に
接続するワイヤ、7はこの半導体装置の機能を外
部に取出すための外部接続用電極(外部ピン)で
ある。
Conventionally, in this type of semiconductor device, multiple semiconductor chips (LSI chips) are planarly mounted on multiple wiring boards, and these wiring boards are sequentially arranged side by side in the stacking direction and mounted on another wiring board. It is known to have a configuration in which these components are provided in a single package. To briefly explain such a conventional three-dimensionally mounted multi-chip package using FIGS. Each of these semiconductor chips 1 has a certain function, such as a large-capacity memory, a large-scale logic circuit of a microprocessor, etc. All the chips 1 constitute the functions of the entire semiconductor device. 2 is a plurality of first wiring boards on which a plurality of these semiconductor chips 1 are arranged and fixed, and their functions are interconnected; 3, these first wiring boards are arranged side by side in an upright state; The first and second wiring boards 2 and 3 are the second wiring boards that interconnect the functions of the multiple semiconductor chips 1.
It is packaged by being placed on an insulating substrate 4 along with the above. Here, in the figure, 5a is an electrode (hereinafter referred to as a bump) made of a Pb-Sn alloy formed on each semiconductor chip 1 for electrically and mechanically connecting it to the first wiring board 2 side, and 5b is an electrode (hereinafter referred to as a bump) on each semiconductor chip 1. An electrode (bump) made of Pb/Sn alloy that electrically and mechanically connects the first wiring board 2 to the second wiring board side.
Further, 6 is a wire that electrically connects the second wiring board 3 and the insulating substrate 4, and 7 is an external connection electrode (external pin) for taking out the function of this semiconductor device to the outside.
このような構成による半導体装置において、半
導体チツプ1の主面に形成したPN接合はAl等に
よる配線(図示せず)で相互に接続され、PN接
合による電気的機能はその主面と同一平面上の任
意の位置から取出される構成とされている。した
がつて、この半導体チツプ1の主面を第1配線基
板2の主面(基板面)と平行して対向配置すれ
ば、その間隙に配置されたバンプ5aをリフロー
ボンデイングすることで、この半導体チツプ1の
機能と第1配線基板2の配線を電気的に接続し、
同時にこの半導体チツプ1を第1配線基板2上に
固定することができるものである。そして、この
第1配線基板2の主面には半導体チツプ1を相互
に接続する配線、相互接続配線(図示せず)が予
め形成されているので、上述したようにして実装
された各半導体チツプ1の機能は互いに接続、複
合される。その結果、この第1配線基板2は、こ
のようにして搭載された複数個の半導体チツプ1
の個数分だけの機能(サブシステム)を構成する
ことになる。 In a semiconductor device with such a configuration, the PN junctions formed on the main surface of the semiconductor chip 1 are connected to each other by wiring (not shown) made of Al or the like, and the electrical functions of the PN junctions are performed on the same plane as the main surface. The structure is such that it can be taken out from any location. Therefore, if the main surface of the semiconductor chip 1 is placed parallel to and facing the main surface (substrate surface) of the first wiring board 2, the semiconductor chip 1 can be bonded by reflow bonding the bumps 5a placed in the gap. electrically connecting the functions of the chip 1 and the wiring of the first wiring board 2;
At the same time, this semiconductor chip 1 can be fixed onto the first wiring board 2. Wiring for interconnecting the semiconductor chips 1 and interconnection wiring (not shown) are formed in advance on the main surface of the first wiring board 2, so that each semiconductor chip mounted as described above The functions of 1 are connected and combined with each other. As a result, this first wiring board 2 has a plurality of semiconductor chips 1 mounted in this way.
This means that as many functions (subsystems) as there are will be configured.
一方、このような複数個の半導体チツプ1を搭
載した第1配線基板2は、第2配線基板3の主面
(基板面)と接触する外周部の一辺に配置した電
極5bをリフローボンデイングすることで、第2
配線基板3の主面上に垂直な立設状態で配置さ
れ、これによりこの第1配線基板2を第2配線基
板3上に電気的に接続し、またこれと同時に機械
的にも固定している。そして、この第2配線基板
3の主面には、第1配線基板2を相互に接続する
配線、相互接続配線(図示せず)が予め形成され
ているため、これに搭載した前記第1配線基板2
上の個々の機能(サブシステム)は互いに接続、
複合されることとなる。したがつて、この第2配
線基板3上に、前記第1配線基板2のサブシステ
ムの全部すなわちこの半導体装置に収納した多数
個の半導体チツプ1のすべての個々の機能を搭載
して複合してなる構成とし得るものである。 On the other hand, in the first wiring board 2 on which a plurality of semiconductor chips 1 are mounted, the electrodes 5b arranged on one side of the outer periphery in contact with the main surface (substrate surface) of the second wiring board 3 are subjected to reflow bonding. So, the second
It is arranged vertically on the main surface of the wiring board 3, thereby electrically connecting the first wiring board 2 to the second wiring board 3, and at the same time mechanically fixing it. There is. Then, on the main surface of this second wiring board 3, wiring for interconnecting the first wiring boards 2 and interconnection wiring (not shown) are formed in advance, so that the first wiring mounted on this Board 2
The individual functions (subsystems) above are connected to each other,
It will be combined. Therefore, on this second wiring board 3, all the subsystems of the first wiring board 2, that is, all the individual functions of the large number of semiconductor chips 1 housed in this semiconductor device are mounted and combined. This can be configured as follows.
また、この第2配線基板3を前記絶縁基板4に
接着剤(図示せず)で機械的に固定した後、第2
配線基板3上に形成した機能取出し用電極(図示
せず)と絶縁基板4上に形成した配線(図示せ
ず)とを、Au等によるワイヤ6で電気的に接続
することによつて、この第2配線基板3の全機能
が絶縁基板4側に継がる。そして、この絶縁基板
4上の配線は、この半導体装置の機能を外部に取
出す外部接続用電極(外部ピン)7に接続されて
いるため、結局半導体チツプ1、バンプ5a、第
1配線基板2、電極5b、第2配線基板3、ワイ
ヤ6、外部ピン7を通じて半導体装置の全機能が
完成し、外部に伝達することが可能となるもので
ある。 Further, after mechanically fixing this second wiring board 3 to the insulating board 4 with an adhesive (not shown), the second wiring board 3 is
This is achieved by electrically connecting the function extracting electrode (not shown) formed on the wiring board 3 and the wiring (not shown) formed on the insulating board 4 with a wire 6 made of Au or the like. All functions of the second wiring board 3 are continued to the insulating board 4 side. Since the wiring on this insulating substrate 4 is connected to an external connection electrode (external pin) 7 that extracts the function of this semiconductor device to the outside, the semiconductor chip 1, the bumps 5a, the first wiring board 2, All functions of the semiconductor device are completed through the electrode 5b, the second wiring board 3, the wire 6, and the external pin 7, and can be transmitted to the outside.
なお、前記絶縁基板4上には、半導体チツプ
1、第1配線基板2、第2配線基板3、ワイヤ6
等を物理的、化学的に保護する蓋体(図示せず)
が被冠して取付けられるので、通常の取扱いでは
この機能が損傷されることはなく、マルチチツプ
パツケージ化された半導体装置として動作される
ものであつた。 Incidentally, on the insulating substrate 4 are a semiconductor chip 1, a first wiring board 2, a second wiring board 3, and a wire 6.
A lid body (not shown) that physically and chemically protects the
Since the device was mounted with a cap on it, this function was not damaged during normal handling, and the device could be operated as a multi-chip packaged semiconductor device.
ところで、上述した従来装置によれば、半導体
チツプ1を搭載した第1配線基板2を、第2配線
基板3の基板面に接触する第1配線基板2外周の
一辺に設けたPb・Sn合金による電極5bによつ
て、この第2配線基板3の基板面上に立設状態で
片持ち式に固定するので、これら第1配線基板2
と第2配線基板3との機械的接続強度は、その電
極5bの設けられていない側の面、すなわち裏面
側から加えられる力に弱い性質をもつていた。こ
れは片持ち式による固定構造上から生じる必然的
な特徴で、振動等の両振り荷重に弱く、信頼度が
低いという欠点に繋がるものであつた。
By the way, according to the conventional device described above, the first wiring board 2 on which the semiconductor chip 1 is mounted is made of a Pb-Sn alloy provided on one side of the outer periphery of the first wiring board 2 in contact with the substrate surface of the second wiring board 3. Since the second wiring board 3 is fixed in a cantilever manner in an upright state on the substrate surface of the second wiring board 3 by the electrodes 5b, these first wiring boards 2
The mechanical connection strength between the electrode 5b and the second wiring board 3 was weak against force applied from the side where the electrode 5b was not provided, that is, the back side. This is an inevitable feature due to the cantilevered fixed structure, and is susceptible to swinging loads such as vibrations, leading to the disadvantage of low reliability.
そして、その一方において、このような機械的
強度を大きくするために電極5bの断面積を大き
くすると、第1配線基板2と第2配線基板3との
接線上に並ぶ電極5b同士が短絡するので、配置
できる電極数を減少させなければならず、これに
より第1配線基板2のサブシステムの信号端子数
を減少させ、結果としてサブシステムの規模を縮
少しなければならないものであつた。また、これ
とは逆に大規模システムを三次元実装マルチチツ
プパツケージに組立てようとすると、電極数が増
加し、電極5bの断面積が減少して両配線基板
2,3間の機械的接続強度が弱くなり、信頼度が
低下するという問題を生じてしまうものであつ
た。 On the other hand, if the cross-sectional area of the electrodes 5b is increased in order to increase the mechanical strength, the electrodes 5b arranged on the tangent between the first wiring board 2 and the second wiring board 3 will short-circuit. However, the number of electrodes that can be arranged must be reduced, thereby reducing the number of signal terminals of the subsystem on the first wiring board 2, and as a result, the scale of the subsystem must be reduced. On the other hand, if a large-scale system is assembled into a three-dimensional multi-chip package, the number of electrodes will increase and the cross-sectional area of the electrode 5b will decrease, thereby increasing the mechanical connection strength between the two wiring boards 2 and 3. This caused the problem that the reliability of the system was weakened and reliability decreased.
すなわち、このような従来装置では、第1配線
基板2と第2配線基板3との機械的強度を大きく
しようとすると、その半導体装置の信頼度が低下
したり、第1配線基板2のサブシステムの規模を
縮少させなければならないという問題をもつもの
で、これらの問題点を一掃し得る何らかの対策を
講じることが望まれている。 That is, in such a conventional device, if an attempt is made to increase the mechanical strength between the first wiring board 2 and the second wiring board 3, the reliability of the semiconductor device may decrease or the subsystem of the first wiring board 2 may deteriorate. There is a problem in that the scale of the problem must be reduced, and it is desired that some kind of measures be taken to eliminate these problems.
本発明は上述した事情に鑑みてなされたもの
で、その装置の信頼度を低下させずに、しかも大
規模システムを構成することが可能となる半導体
装置を得ることを目的としている。 The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to obtain a semiconductor device that can be configured into a large-scale system without reducing the reliability of the device.
本発明に係る半導体装置は、複数個の半導体チ
ツプを基板面上に実装してなる複数枚の第1配線
基板と、これらを立設状態で積層方向に並設する
基板面を有し第1配線基板と直交して配置される
第2配線基板と、この第2配線基板が搭載して固
定され外部接続用電極を有する絶縁基板を備え、
第1配線基板上に実装される半導体チツプのうち
のひとつの側面を、この第1配線基板が立設され
ている第2配線基板の基板面上に接触させるよう
に構成したものである。
A semiconductor device according to the present invention includes a plurality of first wiring boards each having a plurality of semiconductor chips mounted on the board surface, and a board surface on which these wiring boards are arranged in an upright state in parallel in a stacking direction. A second wiring board disposed perpendicular to the wiring board, and an insulating board on which the second wiring board is mounted and fixed and has external connection electrodes,
One side surface of the semiconductor chip mounted on the first wiring board is brought into contact with the surface of the second wiring board on which the first wiring board is erected.
本発明によれば、第2配線基板上に側面が接触
する半導体チツプによつて、この半導体チツプが
実装されている第1配線基板の片持ち式の固定構
造を補強することにより、これら両配線基板間の
機械的接続強度を大きくし得るものである。
According to the present invention, the cantilevered fixing structure of the first wiring board on which the semiconductor chip is mounted is reinforced by the semiconductor chip whose side surface is in contact with the second wiring board. This makes it possible to increase the mechanical connection strength between the substrates.
以下、本発明を図面に示した実施例を用いて詳
細に説明する。
Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.
第1図a,b,c,dは本発明に係る半導体装
置の一実施例を示すものであり、これらの図にお
いて前述した第3図a,b,cと同一または相当
する部分には同一番号を付してその説明は省略す
る。 Figures 1a, b, c, and d show an embodiment of the semiconductor device according to the present invention, and in these figures, the same or corresponding parts as those in Figure 3 a, b, and c described above are the same. They are numbered and their explanations are omitted.
さて、本発明によれば、複数個の半導体チツプ
1と、これら複数個の半導体チツプ1を基板面上
に実装してなる複数枚の第1配線基板2と、これ
ら第1配線基板2を立設状態で積層方向に並設す
る基板面を有し第1配線基板2と直交して配置さ
れる第2配線基板3と、この第2配線基板3が搭
載して固定され外部接続用電極7を有する絶縁基
板4とを備え、第1配線基板2上に実装される半
導体チツプ1のうちのひとつの側面1aを、この
第1配線基板2が立設されている第2配線基板3
の基板面上に接触させるように構成したところに
特徴を有している。 Now, according to the present invention, a plurality of semiconductor chips 1, a plurality of first wiring boards 2 each having a plurality of semiconductor chips 1 mounted on a board surface, and a plurality of first wiring boards 2 are arranged in a vertical position. A second wiring board 3 having board surfaces arranged in parallel in the stacking direction in the installed state and disposed perpendicular to the first wiring board 2; and an external connection electrode 7 on which the second wiring board 3 is mounted and fixed. A side surface 1a of the semiconductor chip 1 mounted on the first wiring board 2 is connected to a second wiring board 3 on which the first wiring board 2 is erected.
The feature is that it is configured to be brought into contact with the surface of the substrate.
すなわち、上述した第1配線基板2に対しバン
プ5aで半導体チツプ1を実装するにあたつて、
少なくともひとつを、その側面1aが第2配線基
板3の基板面上に接するような位置に実装する。
そして、このような第1配線基板2の一側面を第
2配線基板3上に接触させて固定する際に、上述
した半導体チツプ1の側面1aをも第2配線基板
3上に接触させるとよいものである。そして、こ
の状態で前記第1配線基板2の側面を電極5bで
第2配線基板3側に固定すれば、第1配線基板2
側面と半導体チツプ側面1a間の中央部に電極5
bを介在させてなる固定状態が得られるものであ
る。なお、この第2配線基板3はその基板面を電
気的に絶縁しているので、半導体チツプ側面1a
と第2配線基板3とは電気的に独立しており、そ
の機能が損なわれることはない。 That is, when mounting the semiconductor chip 1 with the bumps 5a on the first wiring board 2 described above,
At least one is mounted at a position such that its side surface 1a is in contact with the substrate surface of the second wiring board 3.
When one side surface of the first wiring board 2 is brought into contact with and fixed on the second wiring board 3, it is preferable that the side surface 1a of the semiconductor chip 1 described above is also brought into contact with the second wiring board 3. It is something. In this state, if the side surface of the first wiring board 2 is fixed to the second wiring board 3 side with the electrode 5b, the first wiring board 2
An electrode 5 is provided in the center between the side surface and the semiconductor chip side surface 1a.
A fixed state can be obtained by interposing b. Note that since the second wiring board 3 electrically insulates the board surface, the semiconductor chip side surface 1a
and the second wiring board 3 are electrically independent, and their functions are not impaired.
そして、このような構成において、第1配線基
板2の表面から力を加えると、力点は中央の電極
5b、支点は第1配線基板2の裏面と第2配線基
板3の主面と接触する接線となり、また逆に第1
配線基板2の裏面から力を加えると、力点は同じ
く中央の電極5b、支点は半導体チツプ1の裏面
と第2配線基板3の基板面上に接触する接線とな
る。このときの破断強度は、中央の電極5bの材
料強度に依存するが、半導体チツプ1と第1配線
基板2の厚みは略々同じであることから、これら
両方向からの力に対して略々同程度の機械的接続
強度をもつことになる。つまり、このような本発
明による構造によれば、振動等の両振り荷重に強
くなるように作用する。 In such a configuration, when force is applied from the surface of the first wiring board 2, the point of force is the central electrode 5b, and the fulcrum is the tangent line that contacts the back surface of the first wiring board 2 and the main surface of the second wiring board 3. And conversely, the first
When a force is applied from the back surface of the wiring board 2, the point of force is also the central electrode 5b, and the fulcrum is a tangent that contacts the back surface of the semiconductor chip 1 and the board surface of the second wiring board 3. The breaking strength at this time depends on the material strength of the central electrode 5b, but since the thicknesses of the semiconductor chip 1 and the first wiring board 2 are approximately the same, the breaking strength is approximately the same against forces from both directions. It will have a mechanical connection strength of approximately In other words, the structure according to the present invention acts so as to be strong against swinging loads such as vibrations.
したがつて、本発明による構造では、片持ち式
のように一方向の力に弱いといつた問題はなくな
り、従来のように機械的強度を大きくするため
に、電極5aの断面積を大きくするといつた対策
は不要で、しかも第1配線基板2のサブシステム
の信号端子数を増加させることが可能となり、こ
れにより大規模システムを三次元実装マルチチツ
プパツケージに組立てることが可能となる。 Therefore, in the structure according to the present invention, the problem of being weak against force in one direction as in the cantilever type is eliminated, and unlike the conventional structure, in order to increase mechanical strength, the cross-sectional area of the electrode 5a is increased. No additional countermeasures are required, and the number of signal terminals of the subsystem on the first wiring board 2 can be increased, thereby making it possible to assemble a large-scale system into a three-dimensionally mounted multi-chip package.
第2図は本発明の別の実施例を示すものであつ
て、この実施例では、第2配線基板3上に接する
半導体チツプ1を複数個用いた場合であり、その
作用効果は容易に理解されよう。 FIG. 2 shows another embodiment of the present invention, in which a plurality of semiconductor chips 1 are used in contact with the second wiring board 3, and its effects can be easily understood. It will be.
なお、本発明は上述した実施例構造に限定され
ず、各部の形状、構造等を、適宜変形、変更する
ことは自由である。たとえば上述した実施例で
は、絶縁基板4上に一枚の第2配線基板3を搭載
した場合を説明したが、この絶縁基板4上に複数
枚の第2配線基板3を搭載してもよいことは勿論
である。 Note that the present invention is not limited to the structure of the embodiment described above, and the shape, structure, etc. of each part may be modified and changed as appropriate. For example, in the above-mentioned embodiment, a case was explained in which one second wiring board 3 was mounted on the insulating substrate 4, but a plurality of second wiring boards 3 may be mounted on the insulating board 4. Of course.
さらに、上述した実施例では、半導体チツプ1
を、論理回路LSIチツプとして説明したが、メモ
リ、センサ等の他の機能をもつものであつてもよ
く、またLSIに限らず、MSI、SSIであつてもよ
いことも容易に理解されよう。さらに、半導体チ
ツプ1に能動素子がなく、配線、抵抗、容量等の
受動素子だけが形成されているものでもよく、ま
た半導体チツプ1、第1配線基板2、第2配線基
板3以外にコイル、コンデンサ等の受動素子を搭
載するようにしてもよい。 Furthermore, in the embodiment described above, the semiconductor chip 1
has been described as a logic circuit LSI chip, but it will be easily understood that it may have other functions such as memory and sensor, and it is not limited to LSI but may also be MSI or SSI. Furthermore, the semiconductor chip 1 may have no active elements and only passive elements such as wiring, resistance, and capacitance are formed, and in addition to the semiconductor chip 1, the first wiring board 2, and the second wiring board 3, there may be coils, Passive elements such as capacitors may be mounted.
以上説明したように、本発明に係る半導体装置
によれば、複数個の半導体チツプと、これらを基
板面上に実装してなる複数枚の第1配線基板と、
これら第1配線基板を立設状態で積層方向に並設
する基板面を有し第1配線基板と直交して配置さ
れる第2配線基板と、この第2配線基板が搭載し
て固定され外部接続用電極を有する絶縁基板を備
え、第1配線基板上に実装される半導体チツプの
うちの少なくともひとつの側面を、この第1配線
基板が立設されている第2配線基板の基板面上に
接触させるようにしたので、簡単かつ安価な構成
にもかかわらず、第1配線基板と第2配線基板と
の機械的接続強度を従来に比べ大きくすることが
可能で、これにより振動等の両振り荷重に強くな
り、信頼度を向上させ得るという種々優れた効果
がある。そして、このような本発明によれば、片
持ち式のように一方向への力に弱くないので、機
械的強度を大きくしようとして電極の断面積を大
きくするといつた構成は不要で、第1配線基板の
サブシステムの信号端子数を増加させることも可
能で、これにより大規模システムを三次元実装マ
ルチチツプパツケージに組立てることができる
等、その効果は大きい。
As explained above, according to the semiconductor device according to the present invention, a plurality of semiconductor chips, a plurality of first wiring boards formed by mounting these chips on the substrate surface,
With these first wiring boards standing upright, there is a second wiring board that has board surfaces arranged in parallel in the stacking direction and is arranged orthogonally to the first wiring boards, and a second wiring board that is mounted and fixed to the outside. An insulated substrate having connection electrodes is provided, and at least one side surface of a semiconductor chip mounted on a first wiring board is placed on the substrate surface of a second wiring board on which the first wiring board is erected. By making them contact each other, it is possible to increase the mechanical connection strength between the first wiring board and the second wiring board compared to the conventional method, despite the simple and inexpensive structure. It has various excellent effects such as being resistant to loads and improving reliability. According to the present invention, since it is not weak against force in one direction like a cantilever type, there is no need for a structure in which the cross-sectional area of the electrode is increased in order to increase mechanical strength. It is also possible to increase the number of signal terminals in the wiring board subsystem, which has great effects, such as allowing large-scale systems to be assembled into three-dimensionally mounted multi-chip packages.
第1図a,b,c,dは本発明に係る半導体装
置の一実施例を示す概略斜視図、正面図、側面図
およびそのA部詳細図、第2図は本発明の別の実
施例を示す正面図、第3図a,b,cは従来例を
示す概略斜視図、側面図およびそのB部詳細図で
ある。
1……半導体チツプ、1a……側面、2……第
1配線基板、3……第2配線基板、4……絶縁基
板、5a……バンプ、5b……電極(バンプ)、
6……ワイヤ、7……外部接続用電極。
1a, b, c, and d are schematic perspective views, front views, side views, and a detailed view of part A thereof showing one embodiment of a semiconductor device according to the present invention, and FIG. 2 is another embodiment of the present invention. FIGS. 3A, 3B, and 3C are a schematic perspective view, a side view, and a detailed view of part B of the conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 1a... Side surface, 2... First wiring board, 3... Second wiring board, 4... Insulating substrate, 5a... Bump, 5b... Electrode (bump),
6...Wire, 7...External connection electrode.
Claims (1)
導体チツプを基板面上に実装してなる複数枚の第
1配線基板と、これら第1配線基板を立設状態で
積層方向に並設する基板面を有し前記第1配線基
板と直交して配置される少なくとも一枚の第2配
線基板と、この第2配線基板が搭載して固定され
外部接続用電極を有する絶縁基板とを備え、前記
第1配線基板上に実装される半導体チツプのうち
の少なくともひとつの側面を、この第1配線基板
が立設されている第2配線基板の基板面上に接触
させたことを特徴とする半導体装置。1. A plurality of semiconductor chips, a plurality of first wiring boards formed by mounting these plurality of semiconductor chips on a substrate surface, and a substrate surface on which these first wiring boards are arranged in an upright state in parallel in the stacking direction. at least one second wiring board disposed perpendicularly to the first wiring board; and an insulating board having external connection electrodes on which the second wiring board is mounted and fixed; A semiconductor device characterized in that at least one side surface of a semiconductor chip mounted on a first wiring board is brought into contact with the substrate surface of a second wiring board on which the first wiring board is erected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245824A JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245824A JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6399560A JPS6399560A (en) | 1988-04-30 |
| JPH0531827B2 true JPH0531827B2 (en) | 1993-05-13 |
Family
ID=17139400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61245824A Granted JPS6399560A (en) | 1986-10-15 | 1986-10-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399560A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147411A (en) * | 1998-03-31 | 2000-11-14 | Micron Technology, Inc. | Vertical surface mount package utilizing a back-to-back semiconductor device module |
-
1986
- 1986-10-15 JP JP61245824A patent/JPS6399560A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6399560A (en) | 1988-04-30 |
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