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JPH0533829B2 - - Google Patents
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JPH0533829B2 - - Google Patents

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Publication number
JPH0533829B2
JPH0533829B2 JP61250111A JP25011186A JPH0533829B2 JP H0533829 B2 JPH0533829 B2 JP H0533829B2 JP 61250111 A JP61250111 A JP 61250111A JP 25011186 A JP25011186 A JP 25011186A JP H0533829 B2 JPH0533829 B2 JP H0533829B2
Authority
JP
Japan
Prior art keywords
wiring board
wiring
semiconductor
board
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61250111A
Other languages
Japanese (ja)
Other versions
JPS63104361A (en
Inventor
Myoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61250111A priority Critical patent/JPS63104361A/en
Publication of JPS63104361A publication Critical patent/JPS63104361A/en
Publication of JPH0533829B2 publication Critical patent/JPH0533829B2/ja
Granted legal-status Critical Current

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  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ひとつのパツケージ内に多数個の半
導体チツプを実装してなる、いわゆる三次元実装
マルチチツプパツケージ技術による半導体装置の
改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of a semiconductor device using so-called three-dimensional mounting multi-chip package technology, in which a large number of semiconductor chips are mounted in one package.

〔従来の技術〕[Conventional technology]

従来からこの種の半導体装置として、複数個の
半導体チツプ(LSIチツプ)を、複数枚の配線基
板にそれぞれ平面実装するとともに、これら配線
基板を順次積層方向に並設した状態で別の配線基
板上に設け、さらにこれらをひとつのパツケージ
内に実装してなる構成を有するものが知られてい
る。このような従来の三次元実装マルチチツプパ
ツケージを第2図a,b,cを用いて簡単に説明
すると、図中1はPN接合からなる能動素子およ
びその接続用配線を有し能動、受動機能を備えて
なるSi等による多数個の半導体チツプで、これら
半導体チツプ1はそれぞれがたとえば大容量メモ
リ、マイクロプロセツサの大規模論理回路等の一
定規模の機能を有し、かつこれら多数個の半導体
チツプ1全部でこの半導体装置全体の機能が構成
される。2はこれら多数個の半導体チツプ1が複
数個づつ配置固定されその機能を相互に接続する
複数枚の第1配線基板、3はこれらの第1配線基
板が立設状態で並設されることでその機能を相互
に接続する第2配線基板で、これら第1および第
2配線基板2,3は前記多数個の半導体チツプ1
と共に絶縁基板4上に載置されることでパツケー
ジ化されている。ここで、図中5aは前記各半導
体チツプ1上に形成されこれを第1配線基板2側
に電気的、機械的に接続するためのPb・Sn合金
による電極(以下バンプという)、5bは第1配
線基板2を第2配線基板側に電気的および機械的
に接続するPb・Sn合金による電極(バンプ)で、
また6は第2配線基板3と絶縁基板4を電気的に
接続するワイヤ、7はこの半導体装置の機能を外
部に取出すための外部接続用電極(外部ピン)で
ある。
Conventionally, in this type of semiconductor device, multiple semiconductor chips (LSI chips) are planarly mounted on multiple wiring boards, and these wiring boards are sequentially arranged side by side in the stacking direction and mounted on another wiring board. It is known to have a configuration in which these components are provided in a single package. To briefly explain such a conventional three-dimensional multi-chip package using Fig. 2 a, b, and c, numeral 1 in the figure has an active element consisting of a PN junction and its connection wiring, and has active and passive functions. Each of these semiconductor chips 1 has a certain function, such as a large-capacity memory, a large-scale logic circuit of a microprocessor, etc. All the chips 1 constitute the functions of the entire semiconductor device. 2 is a plurality of first wiring boards on which a plurality of these semiconductor chips 1 are arranged and fixed, and their functions are interconnected; 3, these first wiring boards are arranged side by side in an upright state; The first and second wiring boards 2 and 3 are the second wiring boards that interconnect the functions of the multiple semiconductor chips 1.
It is packaged by being placed on an insulating substrate 4 along with the above. Here, in the figure, 5a is an electrode (hereinafter referred to as a bump) made of a Pb-Sn alloy formed on each semiconductor chip 1 for electrically and mechanically connecting it to the first wiring board 2 side, and 5b is an electrode (hereinafter referred to as a bump) on each semiconductor chip 1. An electrode (bump) made of Pb/Sn alloy that electrically and mechanically connects the first wiring board 2 to the second wiring board side.
Further, 6 is a wire that electrically connects the second wiring board 3 and the insulating substrate 4, and 7 is an external connection electrode (external pin) for taking out the function of this semiconductor device to the outside.

このような構成による半導体装置において、半
導体チツプ1の主面に形成したPN接合はAl等に
よる配線(図示せず)で相互に接続され、PN接
合による電気的機能はその主面と同一平面上の任
意の位置から取出される構成とされている。した
がつて、この半導体チツプ1の主面を第1配線基
板2の主面(基板面)と平行して対向配置すれ
ば、その間隙に配置されたバンプ5aをリフロー
ボンデイングすることで、この半導体チツプ1の
機能と第1配線基板2の配線を電気的に接続し、
同時にこの半導体チツプ1を第1配線基板2上に
固定することができるものである。そして、この
第1配線基板2の主面には半導体チツプ1を相互
に接続する配線、相互接続配線(図示せず)が予
め形成されているので、上述したようにして実装
された各半導体チツプ1の機能は互いに接続、複
合される。その結果、この第1配線基板2は、こ
のようにして搭載された複数個の半導体チツプ1
の個数分だけの機能(サブシステム)を構成する
ことになる。
In a semiconductor device with such a configuration, the PN junctions formed on the main surface of the semiconductor chip 1 are connected to each other by wiring (not shown) made of Al or the like, and the electrical functions of the PN junctions are performed on the same plane as the main surface. The structure is such that it can be taken out from any location. Therefore, if the main surface of the semiconductor chip 1 is placed parallel to and facing the main surface (substrate surface) of the first wiring board 2, the semiconductor chip 1 can be bonded by reflow bonding the bumps 5a placed in the gap. electrically connecting the functions of the chip 1 and the wiring of the first wiring board 2;
At the same time, this semiconductor chip 1 can be fixed onto the first wiring board 2. Wiring for interconnecting the semiconductor chips 1 and interconnection wiring (not shown) are formed in advance on the main surface of the first wiring board 2, so that each semiconductor chip mounted as described above The functions of 1 are connected and combined with each other. As a result, this first wiring board 2 has a plurality of semiconductor chips 1 mounted in this way.
This means that the number of functions (subsystems) is as many as the number of functions (subsystems).

一方、このような複数個の半導体チツプ1を搭
載した第1配線基板2は、第2配線基板3の主面
(基板面)と接触する外周部の一辺に配置した電
極5bをリフローボンデイングすることで、第2
配線基板3の主面上に垂直な立設状態で配置さ
れ、これによりこの第1配線基板2を第2配線基
板3上に電気的に接続し、またこれと同時に機械
的にも固定している。そして、この第2配線基板
3の主面には、第1配線基板2を相互に接続する
配線、相互接続配線(図示せず)が予め形成され
ているため、これに搭載した前記第1配線基板2
上の個々の機能(サブシステム)は互いに接続、
複合されることとなる。したがつて、この第2配
線基板3上に、前記第1配線基板2のサブシステ
ムの全部すなわちこの半導体装置に収納した多数
個の半導体チツプ1のすべての個々の機能を搭載
して複合してなる構成とし得るものである。
On the other hand, in the first wiring board 2 on which a plurality of such semiconductor chips 1 are mounted, the electrodes 5b arranged on one side of the outer periphery in contact with the main surface (substrate surface) of the second wiring board 3 are subjected to reflow bonding. So, the second
It is disposed vertically on the main surface of the wiring board 3, thereby electrically connecting the first wiring board 2 to the second wiring board 3, and at the same time mechanically fixing it. There is. Then, on the main surface of this second wiring board 3, wiring for interconnecting the first wiring boards 2 and interconnection wiring (not shown) are formed in advance, so that the first wiring mounted on this Board 2
The individual functions (subsystems) above are connected to each other,
It will be combined. Therefore, on this second wiring board 3, all the subsystems of the first wiring board 2, that is, all the individual functions of the large number of semiconductor chips 1 housed in this semiconductor device are mounted and combined. This can be configured as follows.

また、この第2配線基板3を前記絶縁基板4に
接着剤(図示せず)で機械的に固定した後、第2
配線基板3上に形成した機能取出し用電極(図示
せず)と絶縁基板4上に形成した配線(図示せ
ず)とを、Au等によるワイヤ6で電気的に接続
することによつて、この第2配線基板3の全機能
が絶縁基板4側に継がる。そして、この絶縁基板
4上の配線は、この半導体装置の機能を外部に取
出す外部接続用電極(外部ピン)7に接続されて
いるため、結局半導体チツプ1、バンプ5a、第
1配線基板2、電極5b、第2配線基板3、ワイ
ヤ6、外部ピン7を通じて半導体装置の全機能が
完成し、外部に伝達することが可能となるもので
ある。
Further, after mechanically fixing this second wiring board 3 to the insulating board 4 with an adhesive (not shown), the second wiring board 3 is
This is achieved by electrically connecting the function extracting electrode (not shown) formed on the wiring board 3 and the wiring (not shown) formed on the insulating board 4 with a wire 6 made of Au or the like. All functions of the second wiring board 3 are continued to the insulating board 4 side. Since the wiring on this insulating substrate 4 is connected to an external connection electrode (external pin) 7 that extracts the function of this semiconductor device to the outside, the semiconductor chip 1, the bumps 5a, the first wiring board 2, All functions of the semiconductor device are completed through the electrode 5b, the second wiring board 3, the wire 6, and the external pin 7, and can be transmitted to the outside.

なお、前記絶縁基板4上には、半導体チツプ
1、第1配線基板2、第2配線基板3、ワイヤ6
等を物理的、化学的に保護する蓋体(図示せず)
が被冠して取付けられるので、通常の取扱いでは
この機能が損傷されることはなく、マルチチツプ
パツケージ化された半導体装置として動作される
ものであつた。
Incidentally, on the insulating substrate 4 are a semiconductor chip 1, a first wiring board 2, a second wiring board 3, and a wire 6.
A lid body (not shown) that physically and chemically protects the
Since the device was mounted with a cap on it, this function was not damaged during normal handling, and the device could be operated as a multi-chip packaged semiconductor device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上述した従来装置によれば、半導体
チツプ1の主面を、第1配線基板2の基板面に平
行して配置させており、このような構造では、半
導体チツプ1を搭載した第1配線基板2の基板当
りの厚みは、第1配線基板2の厚みと半導体チツ
プ1およびバンプ5aの厚みの和となつている。
そして、第1配線基板2は、一般には、半導体チ
ツプ1と同じ形状の材料を用いて加工するので、
バンプ5aの厚みを無視すれば、その厚みの半分
が第1配線基板2、残り半分が半導体チツプ1分
となる。つまり、この第1配線基板2に含まれる
半導体チツプ1の割合が50%となつている。そし
て、この第1配線基板2に含まれる半導体チツプ
1の割合が、この半導体装置における半導体チツ
プ1実装密度(半導体装置内に含まれる半導体チ
ツプ数/半導体装置体積)を決定する。したがつ
て、この密度を向上させるには、第1配線基板2
の厚みを半導体チツプ1の厚みよりも薄くしなけ
ればならない。しかしながら、第1配線基板2の
厚みを薄くすれば、半導体チツプ1を支えるため
の機械的強度が低下し、これにより装置製造工程
における良品歩留りが悪くなり、結局第1配線基
板2に含まれる半導体チツプ1の割合を50%以上
にすることがきわめて困難であるという欠点があ
つた。
By the way, according to the conventional device described above, the main surface of the semiconductor chip 1 is arranged parallel to the substrate surface of the first wiring board 2, and in such a structure, the first wiring on which the semiconductor chip 1 is mounted The thickness of the substrate 2 per substrate is the sum of the thickness of the first wiring board 2 and the thickness of the semiconductor chip 1 and the bumps 5a.
Since the first wiring board 2 is generally processed using a material having the same shape as the semiconductor chip 1,
If the thickness of the bumps 5a is ignored, half of the thickness will be the first wiring board 2, and the remaining half will be the semiconductor chip. In other words, the proportion of semiconductor chips 1 included in this first wiring board 2 is 50%. The proportion of semiconductor chips 1 included in this first wiring board 2 determines the semiconductor chip 1 packaging density (number of semiconductor chips included in the semiconductor device/semiconductor device volume) in this semiconductor device. Therefore, in order to improve this density, the first wiring board 2
The thickness of the semiconductor chip 1 must be made thinner than the thickness of the semiconductor chip 1. However, if the thickness of the first wiring board 2 is reduced, the mechanical strength for supporting the semiconductor chip 1 will be reduced, which will reduce the yield of non-defective products in the device manufacturing process. The drawback was that it was extremely difficult to increase the proportion of chip 1 to 50% or more.

本発明は上述した事情に鑑みてなされたもの
で、製造工程における良品歩留りを低下させず
に、しかも第1配線基板に含まれる半導体チツプ
の割合を増加させることが可能となる半導体装置
を得ることを目的としている。
The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to obtain a semiconductor device in which it is possible to increase the proportion of semiconductor chips included in a first wiring board without reducing the yield of non-defective products in the manufacturing process. It is an object.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る半導体装置は、複数個の半導体チ
ツプを基板面上に実装してなる複数枚の第1配線
基板と、これらを立設状態で積層方向に並設する
基板面を有し第1配線基板と直交して配置される
第2配線基板と、この第2配線基板が搭載して固
定され外部接続用電極を有する絶縁基板を備え、
複数個の半導体チツプを、その主面が第1配線基
板の基板面に交差する角度をもつようにして互い
に積層方向に並設させて実装するようにしたもの
である。
A semiconductor device according to the present invention includes a plurality of first wiring boards each having a plurality of semiconductor chips mounted on the board surface, and a board surface on which these wiring boards are arranged in an upright state in parallel in a stacking direction. A second wiring board disposed perpendicular to the wiring board, and an insulating board on which the second wiring board is mounted and fixed and has external connection electrodes,
A plurality of semiconductor chips are mounted side by side in the stacking direction so that their main surfaces intersect with the substrate surface of the first wiring board.

〔作用〕[Effect]

本発明によれば、半導体チツプを搭載した第1
配線基板の基板当りの厚みが、第1配線基板の厚
みと半導体チツプの主面寸法の一辺とバンプの厚
みとの和となり、そのほとんどを半導体チツプで
占めることになり、これにより基板当りの半導体
チツプの割合を増加させることができ、装置全体
での実装密度を向上させ得るものである。
According to the present invention, the first
The thickness of the wiring board per board is the sum of the thickness of the first wiring board, one side of the main surface of the semiconductor chip, and the thickness of the bumps, and most of the thickness is occupied by the semiconductor chip. The chip ratio can be increased, and the packaging density of the entire device can be improved.

〔実施例〕〔Example〕

以下、本発明を図面に示した実施例を用いて詳
細に説明する。
Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

第1図a,b,c,dは本発明に係る半導体装
置の一実施例を示すものであり、これらの図にお
いて前述した第2図a,b,cと同一または相当
する部分には同一番号を付してその説明は省略す
る。
Figures 1a, b, c, and d show one embodiment of a semiconductor device according to the present invention, and in these figures, the same or corresponding parts as those in Figure 2 a, b, and c described above are the same. They are numbered and their explanations are omitted.

さて、本発明によれば、複数個の半導体チツプ
1と、これら複数個の半導体チツプ1を基板面上
に実装してなる複数枚の第1配線基板2と、これ
ら第1配線基板2を立設状態で積層方向に並設す
る基板面を有し第1配線基板2と直交して配置さ
れる第2配線基板3と、この第2配線基板3が搭
載して固定され外部接続用電極7を有する絶縁基
板4とを備え、複数個の半導体チツプを、その主
面が第1配線基板の基板面に交差する角度をもつ
ようにして互いに積層方向に並設させて実装する
ようにしたところに特徴を有している。
Now, according to the present invention, a plurality of semiconductor chips 1, a plurality of first wiring boards 2 each having a plurality of semiconductor chips 1 mounted on a board surface, and a plurality of first wiring boards 2 are arranged in a vertical position. A second wiring board 3 having board surfaces arranged in parallel in the stacking direction in the installed state and disposed perpendicular to the first wiring board 2; and an external connection electrode 7 on which the second wiring board 3 is mounted and fixed. A plurality of semiconductor chips are mounted side by side in the stacking direction so that their main surfaces intersect with the substrate surface of the first wiring board. It has the following characteristics.

すなわち、本実施例では、上述した半導体チツ
プ1を、その主面が基板面に直交するようにして
第1配線基板2に実装した場合を示している。そ
して、このようにして実装された半導体チツプ1
は、その接合部分に設けたバンプ5aにより電気
的に接続されるとともに、機械的にも固定して保
持されることは勿論である。
That is, this embodiment shows the case where the above-described semiconductor chip 1 is mounted on the first wiring board 2 with its main surface perpendicular to the substrate surface. The semiconductor chip 1 mounted in this way
Needless to say, these are not only electrically connected by the bumps 5a provided at the joint portions but also mechanically fixed and held.

このような構成によれば、半導体チツプ1を実
装した第1配線基板2の基板当りの厚みは、この
第1配線基板2の厚みと半導体チツプ1の主面寸
法の一辺(たとえば10mm角の半導体チツプであれ
ば10mm)とバンプ5aの厚み(たとえば0.1mm)
の和となる。そして、第1配線基板2の厚みは一
般に半導体チツプ1の厚みと同じでかつ薄い(た
とえば各々0.5mm)ので、第1配線基板2の厚み
のその大部分を、半導体チツプ1の主面寸法の一
辺が占めることになる(10/11.1=0.90)。これ
は、第1配線基板2の基板当りの厚みの大部分を
半導体チツプ1が占めていることを示している。
したがつて、このような構成を採用すれば、第1
配線基板2に含まれる半導体チツプ1の割合を増
加させることができ、その実装密度を増大させ得
るものである。また、第1配線基板2の厚みを薄
くしないので、第1配線基板2の機械的強度は低
下せず、装置製造工程における良品歩留りを低下
させるといつた問題は解消される。
According to such a configuration, the thickness per board of the first wiring board 2 on which the semiconductor chip 1 is mounted is the thickness of the first wiring board 2 and one side of the main surface dimension of the semiconductor chip 1 (for example, a 10 mm square semiconductor If it is a chip, it is 10mm) and the thickness of the bump 5a (for example, 0.1mm)
is the sum of Since the thickness of the first wiring board 2 is generally the same as the thickness of the semiconductor chip 1 and thin (for example, 0.5 mm each), most of the thickness of the first wiring board 2 is equal to the main surface dimension of the semiconductor chip 1. One side will be occupied (10/11.1=0.90). This indicates that the semiconductor chip 1 occupies most of the thickness of the first wiring board 2 per board.
Therefore, if such a configuration is adopted, the first
The proportion of semiconductor chips 1 included in the wiring board 2 can be increased, and the packaging density thereof can be increased. Further, since the thickness of the first wiring board 2 is not reduced, the mechanical strength of the first wiring board 2 is not reduced, and the problem of lowering the yield of good products in the device manufacturing process is solved.

ここで、このような作用効果は、上述した半導
体チツプ1が第1配線基板2に対して直交して実
装されている場合以外にも同様に作用するもの
で、要は互いに積層方向に並設した状態で、半導
体チツプ1をその主面が第1配線基板2の基板面
に交差する角度をもつようにして設けるとよいも
のである。
Here, such an effect is similarly exerted even when the semiconductor chips 1 described above are mounted orthogonally to the first wiring board 2, and in short, when the semiconductor chips 1 are mounted parallel to each other in the stacking direction. It is preferable to install the semiconductor chip 1 in such a state that its main surface has an angle intersecting the substrate surface of the first wiring board 2.

なお、本発明は上述した実施例構造に限定され
ず、各部の形状、構造等を、適宜変形、変更する
ことは自由である。たとえば上述した実施例で
は、絶縁基板4上に一枚の第2配線基板3を搭載
した場合を説明したが、この絶縁基板4上に複数
枚の第2配線基板3を搭載してもよいことは勿論
である。
Note that the present invention is not limited to the structure of the embodiment described above, and the shape, structure, etc. of each part may be modified and changed as appropriate. For example, in the above-mentioned embodiment, a case was explained in which one second wiring board 3 was mounted on the insulating substrate 4, but a plurality of second wiring boards 3 may be mounted on the insulating board 4. Of course.

さらに、上述した実施例では、半導体チツプ1
を、論理回路LSIチツプとして説明したが、メモ
リ、センサ等の他の機能をもつものであつてもよ
く、またLSIに限らず、MSI,SSIであつてもよ
いことも容易に理解されよう。さらに、半導体チ
ツプ1に能動素子がなく、配線、抵抗、容量等の
受動素子だけが形成されているものでもよく、ま
た半導体チツプ1、第1配線基板2、第2配線基
板3以外にコイル、コンデンサ等の受動素子を搭
載するようにしてもよい。
Furthermore, in the embodiment described above, the semiconductor chip 1
has been described as a logic circuit LSI chip, but it is easy to understand that it may have other functions such as memory and sensor, and it is not limited to LSI, but may also be MSI or SSI. Furthermore, the semiconductor chip 1 may have no active elements and only passive elements such as wiring, resistance, and capacitance are formed, and in addition to the semiconductor chip 1, the first wiring board 2, and the second wiring board 3, there may be coils, Passive elements such as capacitors may be mounted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明に係る半導体装置
によれば、複数個の半導体チツプと、これらを基
板面上に実装してなる複数枚の第1配線基板と、
これら第1配線基板を立設状態で積層方向に並設
する基板面を有し第1配線基板と直交して配置さ
れる第2配線基板と、この第2配線基板が搭載し
て固定され外部接続用電極を有する絶縁基板を備
え、複数個の半導体チツプを、その主面が第1配
線基板の基板面に交差する角度をもつようにして
互いに積層方向に並設させて実装するようにした
ので、簡単かつ安価な構成にもかかわらず、第1
配線基板の基板当りの厚みの大部分を半導体チツ
プの主面寸法の一辺が占めることになり、これに
より第1配線基板に含まれる半導体チツプの割合
を増加させることができ、その実装密度を増大さ
せ得るとともに、所要の機械的強度を第1配線基
板にもたせ、製造工程における良品歩留りを一定
の状態に維持することができ、その結果三次元実
装マルチチツプモジユールのプロセス上の困難性
を増大させずに、実装密度を向上させ得る等とい
つた種々優れた効果がある。
As explained above, according to the semiconductor device according to the present invention, a plurality of semiconductor chips, a plurality of first wiring boards formed by mounting these chips on the substrate surface,
With these first wiring boards in an upright state, a second wiring board having board surfaces arranged in parallel in the stacking direction and arranged orthogonally to the first wiring boards, and a second wiring board mounted and fixed on the outside. An insulating substrate having connection electrodes is provided, and a plurality of semiconductor chips are mounted side by side in the stacking direction so that their main surfaces intersect with the substrate surface of the first wiring board. Therefore, despite the simple and inexpensive configuration, the first
One side of the main surface of the semiconductor chip occupies most of the thickness per board of the wiring board, which makes it possible to increase the proportion of semiconductor chips included in the first wiring board, increasing its packaging density. At the same time, it is possible to provide the first wiring board with the necessary mechanical strength and maintain a constant yield of good products in the manufacturing process, which increases the difficulty in the process of three-dimensionally mounted multi-chip modules. There are various excellent effects such as improving the packaging density without increasing the cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,b,c,dは本発明に係る半導体装
置の一実施例を示す概略斜視図、正面図、側面図
およびそのA部詳細図、第2図a,b,cは従来
例を示す概略斜視図、側面図およびそのB部詳細
図である。 1……半導体チツプ、2……第1配線基板、3
……第2配線基板、4……絶縁基板、5a……バ
ンプ、5b……電極(バンプ)、6……ワイヤ、
7……外部接続用電極。
FIGS. 1 a, b, c, and d are schematic perspective views, front views, side views, and a detailed view of part A thereof showing one embodiment of the semiconductor device according to the present invention, and FIGS. 2 a, b, and c are conventional examples. They are a schematic perspective view, a side view, and a detailed view of part B thereof. 1... Semiconductor chip, 2... First wiring board, 3
...Second wiring board, 4...Insulating substrate, 5a...Bump, 5b...Electrode (bump), 6...Wire,
7...External connection electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 複数個の半導体チツプと、これら複数個の半
導体チツプを基板面上に実装してなる複数枚の第
1配線基板と、これら第1配線基板を立設状態で
積層方向に並設する基板面を有し前記第1配線基
板と直交して配置される少なくとも一枚の第2配
線基板と、この第2配線基板が搭載して固定され
外部接続用電極を有する絶縁基板とを備え、前記
複数個の半導体チツプは、その主面が第1配線基
板の基板面に交差する角度をもつようにして互い
に積層方向に並設されて実装されていることを特
徴とする半導体装置。
1. A plurality of semiconductor chips, a plurality of first wiring boards formed by mounting these plurality of semiconductor chips on a substrate surface, and a substrate surface on which these first wiring boards are arranged in an upright state in parallel in the stacking direction. at least one second wiring board disposed perpendicularly to the first wiring board; and an insulating board having external connection electrodes on which the second wiring board is mounted and fixed; 1. A semiconductor device characterized in that the semiconductor chips are mounted in parallel with each other in the stacking direction so that their main surfaces intersect with the substrate surface of the first wiring board.
JP61250111A 1986-10-20 1986-10-20 Semiconductor device Granted JPS63104361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61250111A JPS63104361A (en) 1986-10-20 1986-10-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61250111A JPS63104361A (en) 1986-10-20 1986-10-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63104361A JPS63104361A (en) 1988-05-09
JPH0533829B2 true JPH0533829B2 (en) 1993-05-20

Family

ID=17202988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61250111A Granted JPS63104361A (en) 1986-10-20 1986-10-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63104361A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
JP3461204B2 (en) * 1993-09-14 2003-10-27 株式会社東芝 Multi-chip module

Also Published As

Publication number Publication date
JPS63104361A (en) 1988-05-09

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