JPH0533810B2 - - Google Patents

Description

[Detailed description of the invention]

<Industrial Application Field> The present invention relates to a method for forming a compound semiconductor layer, and particularly to a method for forming a high quality GaAs compound semiconductor layer on a silicon substrate using a silicon substrate. <Conventional technology> Compound semiconductors such as GaAs and InP are being used for high performance and high functionality devices by taking advantage of their excellent characteristics. However, compound semiconductor crystals are generally expensive, and problems such as difficulty in obtaining large-area, high-quality substrate crystals remain unsolved. In an attempt to overcome these problems, we used cheap, high-quality, and lightweight silicon as a substrate, stacked compound semiconductor layers on this silicon substrate, and then constructed the aforementioned devices on the stacked compound semiconductor layers. Attempts have been made to manufacture semiconductor devices. Although several methods for manufacturing compound semiconductor devices using such silicon substrates have been proposed, they are still inferior to bulk crystals in terms of crystal quality and the like. For example, the following methods are currently being attempted to form a single crystal GaAs layer on a silicon (Si) substrate. That is, when forming a GaAs layer on a silicon (Si) substrate, it is a so-called two-step growth method in which a preliminary deposition layer is formed in advance, and then GaAs is epitaxially grown under normal growth conditions. The preliminary deposition layer can be a GaAs layer, a Ge layer, or a GaAsP and GaP layer formed at a lower temperature than normal growth conditions.
A buffer layer in which GaAs and GaAs are alternately laminated is used. As an example, the growth process using a two-step growth method using a GaAs layer as a preliminary deposition layer will be described below. First, a film of about 100 Å was deposited on a silicon (Si) substrate using MOCVD or MBE at a temperature below 450°C.
After forming a GaAs layer, the substrate is heated to a normal GaAs epitaxial growth temperature (600°C to 750°C), and then a GaAs layer is grown. FIG. 3 is a schematic diagram showing the structure of a GaAs layer 2 on a silicon (Si) substrate 1 obtained by a two-step growth method, and 3 is a preliminary deposited layer. No matter which of the above-mentioned materials is used as the predeposition layer 3, in the interface region between Si and GaAs, the Si and GaAs
The difference in the lattice constants of GaAs (~4%) generates a high density of mismatched dislocations, some of which propagate in the growth direction during growth and penetrate the grown layer. In particular, the stress caused by the large difference in expansion coefficient between the silicon (Si) substrate 1 and the GaAs layer 2 during cooling from the growth temperature to room temperature after the completion of growth greatly promotes the propagation of dislocations in the growth direction. When reaching the active layer formation region and manufacturing a device on the GaAs layer 2, it has the greatest effect on device performance. The density of mismatched dislocations generated in the interface region between Si and GaAs is approximately 10 ¹⁰ cm ^-2 , and the density of dislocations that have reached the GaAs surface after stacking 3 μm of GaAs is approximately 10 ⁸ cm
^-2 , based on observation using a transmission electron microscope (TEM) and measurements of etching pitch density (EPD) using molten KOH. Dislocations act as recombination centers for minority carriers, causing a significant decrease in minority carrier lifetime in crystals with high density dislocations. Therefore, the performance of a compound semiconductor device using minority carriers is significantly degraded. As a method for reducing this high-density dislocation, Tsaur et al. proposed a combination of growth interruption and thermal cycling (thermal cycling growth method) (16th, IEEE PVSC, 1982). FIG. 4 is a diagram showing an example of a temperature program based on this thermal cycle growth method. Also, Figure 5 A~
C is a diagram for explaining one cycle of this thermal cycle growth method, in which a silicon (Si) substrate 1
The upper part shows a case where Ge is used as the preliminary deposit layer 3, and FIG. When the growth is interrupted as shown in Figure B, the substrate temperature is lowered from 700°C to room temperature, and dislocation loops are formed by interaction between dislocations, and in the subsequent second growth layer 22 (Figure 5C), dislocations are reduced. are doing. Furthermore, they confirmed the dislocation reduction effect only after repeating the process shown in FIGS. 5A to 5C more than 10 times. <Problems to be Solved by the Invention> However, when the above conventionally proposed process is actually applied to manufacturing, the growth layer formed by repeating thermal cycles (hereinafter referred to as a thermal cycle layer) is Until now, it has not been clarified where to form a compound semiconductor growth layer on a silicon (Si) substrate to efficiently obtain a high-quality active layer. A thermal cycle layer is formed immediately from the interface between the substrate and the compound semiconductor layer, and in this case, the expected reduction in dislocation density may not be achieved.
In addition, in order to sufficiently reduce dislocation density, the number of thermal cycles was set to 20 or more.
In this case, there was a manufacturing problem in that the time required for thermal cycle growth was significantly increased. That is,
For example, when using high-frequency heating and water-cooled reaction tube type organic metal vapor deposition (MOCVD) methods, which are said to have relatively short heating and cooling times, GaAs The time required to form a growth layer is about 1 hour, compared to the time required to perform 20 thermal cycles.
It takes more than a few hours, and there is a big manufacturing problem in terms of efficiency with respect to time. The present invention was created in view of the above points,
The purpose of the present invention is to provide a new and improved method for forming a compound semiconductor layer that solves the problems of the thermal cycle growth method in order to improve the quality of the grown layer when growing the compound semiconductor layer on a silicon substrate. There is. <Means and effects for solving the problems> In order to achieve the above-mentioned object, the method for forming a compound semiconductor layer of the present invention does not involve a temperature cooling cycle when growing a GaAs compound semiconductor layer on a silicon substrate. A first step of continuously growing a compound semiconductor layer to form a compound semiconductor layer by the first continuous growth; By repeating the interruption and temperature reduction during the interruption, a compound semiconductor layer conductor layer is successively grown in each cycle on the compound semiconductor layer formed by the first continuous growth, and a compound semiconductor layer is formed by the second thermal cycle. a second step of forming the compound semiconductor layer formed by the second thermal cycle through the compound semiconductor layer formed by the first continuous growth, and at least an upper end of the compound semiconductor layer formed by the second thermal cycle forming It is characterized by being formed at a position exceeding 1.9 μm from the interface of the substrate. That is, in a method for forming a compound semiconductor layer on a silicon (Si) substrate, the present invention suppresses the propagation of mismatched dislocations existing between the substrate and the compound semiconductor layer and dislocations caused by thermal stress by controlling the propagation of dislocations at the upper end of the compound semiconductor layer due to thermal cycles. By forming the compound semiconductor layer by continuous growth without thermal cycling, which is performed before the formation of the compound semiconductor layer by thermal cycling, the compound semiconductor layer can be confined near the interface in a shorter time and more efficiently than conventional methods, and the upper layer can be By reducing dislocations in the active layer formation region of compound semiconductor devices, high quality and
This is a method for improving the crystallinity of a grown layer by applying thermal stress during growth, which is used in the present invention, to provide a compound semiconductor device that can be made low-cost and lightweight. can be understood as follows. That is, since the generation and propagation of dislocations are promoted by local stress concentration, thermal stress based on the difference in thermal expansion coefficient between the silicon (Si) substrate and the GaAs layer is applied to the grown layer during cooling after the growth is interrupted. The dislocations near the pre-deposited layer are propagated to the surface of the crystal layer and release part of the thermal stress in the crystal. After raising the temperature again,
When a 2GaAs layer is grown and the temperature is lowered, the dislocations in the first growth layer may form loops with each other, or point defects caused by impurities present in the growth layer may stick on the dislocations, causing dislocation propagation. is prevented (this is called dislocation immobilization). In this way, the dislocation density propagating to the second growth layer is
It is possible to reduce it compared to that in the layer. Therefore, dislocations reach the active layer region near the growth surface by repeatedly forcibly forming dislocation loops by applying thermal stress to the growing layer when the temperature is lowered, and immobilizing the dislocations by reducing the thermal stress when the temperature is rising. This makes it possible to reduce the Based on the above understanding, the present invention aims to select the formation position of the thermal cycle layer that is most effective for forming dislocation loops and immobilizing dislocations by forcibly introducing dislocations, and for reducing dislocations near the interface of the silicon substrate. Considering that a cycle layer is not necessarily required, we aim to improve the quality of a compound semiconductor growth layer on a silicon substrate efficiently in a relatively short growth time, and use it as a substrate that can produce high-performance compound semiconductor devices. The thermal cycle layer is formed on the silicon substrate via a compound semiconductor layer that is continuously grown, and the upper end of the thermal cycle layer is at least 1.9 μm away from the interface of the silicon substrate. It is characterized by being formed in such a way that it lies in the correct position. That is, the present invention has found that thermal cycle growth up to approximately 1.9 μm from the interface between the silicon substrate and the compound semiconductor layer hardly contributes to improvement of crystal quality, and therefore, the thermal cycle growth is not formed near the interface, and By arranging the upper end of the thermal cycle layer at a distance of at least 1.9 .mu.m from the surface, the quality of the compound semiconductor layer on the silicon substrate can be improved in a short time and efficiently. <Examples> The present invention will be described in detail below based on Examples. Note that although the following example describes the formation of a GaAs semiconductor layer, the present invention is not limited to this example.
The scope of application is not limited to the MOCVD method at a temperature of 700°C, but any method and temperature that can grow compound semiconductors such as the MBE method or halogen transport method can be similarly applied. Needless to say. Example 1 Two-step growth was performed by MOCVD using a high-frequency heating/water-cooled reaction tube, and on a Si(100) substrate,
First, as a pre-deposition layer, about 100
After forming a GaAs layer with a thickness of 1.5 Å, the temperature of the substrate is raised to the normal GaAs epitaxial growth temperature (600°C to 750°C), and a GaAs layer including a thermal cycle layer is grown in the middle. The dislocation density near the surface was evaluated using planar TEM or EPD measurement method using molten KOH. As an example of applying the thermal cycle conditions of the present invention, as shown in FIG.
After forming the layer (not shown in the figure because it is a thin layer), the
The thickness of the GaAs layer 32 is 2.6 μm without a cooling cycle.
The film is grown to a thickness of . This 2.6μm GaAs layer 32
is a semiconductor layer formed by continuous growth. Next, in order to shorten the growth stop time, the lower limit temperature of the thermal cycle was set to 300°C, and the initial cooling rate was set to about 2°C/sec.
The upper limit temperature for heating is 700℃, and 10
1.0μ by performing a temperature-lowering/heating-up heat cycle.
A thermal cycle layer 33 with a thickness of m is placed on a silicon substrate 31.
At least in the growth direction from the interface between
Formed at a distance exceeding 1.9μm, and further 1.0μm
A GaAs layer 34 of 200 nm was laminated at a growth temperature of 700° C., and the dislocation density near the surface of the grown layer was measured. For comparison, under conventional thermal cycle conditions, a GaAs layer 42 (the preliminary deposited layer is similarly omitted; the same applies hereinafter) is grown on a silicon (Si) substrate 41 in two steps as shown in FIG. The film was grown to a thickness of 0.1 μm, and then the lower limit temperature of the thermal cycle was set.
90℃, upper temperature increase temperature 700℃, growth layer thickness 0.1μ
A thermal cycle layer 43 with a thickness of 1.0 μm is formed by carrying out a thermal cycle of 10 temperature-lowering/temperature-increasing cycles every m, and the distance from the interface between the silicon substrate 41 and the GaAs layer 42 to the upper end of the thermal cycle layer 43 is 1.3 μm or less, and then a 1.0 μm GaAs layer 44 with a thickness of 700 μm.
The layers were stacked at a growth temperature of °C, and the dislocation density near the surface of the grown layer was measured. Table 1 compares the measured dislocation densities near the surface of the GaAs growth layer of the substrates having the structures shown in FIGS. 1 and 6 above.

[Table] As is clear from Table 1, the dislocation density was 7.9×10 7 cm -2 for sample (a) in which the thermal cycle was performed without selecting the optimal position, whereas the dislocation density of the method of the present invention was 7.9×10 ⁷ cm ^-2 . Accordingly, the thermal cycle growth method was carried out at a position at least 1.9 μm in the growth direction from the interface of the GaAs layer 2 of the silicon substrate 1, so that the distance to the top of the thermal cycle layer 3 was 3.6 μm. For (b), the dislocation density was 8.2×10 ⁶ cm ^-2 , which was about an order of magnitude lower than the conventional method. Example 2 In Example 1 described above, the effect of reducing the dislocation density by the method of the present invention was demonstrated by changing the distance to the top of the thermal cycle layer. However, as an example of application to actual device fabrication, With the thickness fixed at 3 μm, n-GaAs is first grown on an n-silicon (Si) substrate 51 in two steps as shown in FIG.
The layer 52 was grown to a thickness of 0.9 μm without a temperature-lowering cycle, and then a thermal cycle layer with a total thickness of 1.0 μm was grown for 10 cycles, each layer having a thickness of 0.1 μm, under the same thermal cycle conditions as in Example 1. (n-GaAs layer) 53 is grown, and an n-GaAs layer 54 with a thickness of 0.8 μm is further grown.
A p-GaAs layer 55 with a thickness of 0.3 μm was formed in this order, and an N-side electrode 56 and a P-side electrode 57 were formed at both ends. In this way, a p/n junction with a depth of 0.3 μm was formed as an active layer on the surface side of the thermal cycle layer 53 (carrier concentration p ~ 2×10 ¹⁸ cm ^-3 , n ~ 1×10 ¹⁷ cm ^-3 )
The current-voltage characteristics of the diode in the dark state were measured. For comparison, as shown in FIG. 7, a 0.3μ
An n-GaAs layer 62 with a thickness of m is grown, and then
1.0 μm thick n-GaAs layer (thermal cycle layer) 6
3 was grown, and further an n-GaAs layer 64 with a layer thickness of 1.4 μm and a p-GaAs layer 65 with a layer thickness of 0.3 μm were formed in this order, and an N-side electrode 66 and a P-side electrode 6 were formed on both ends.
As shown in FIG. 8, an n-GaAs layer 74 with a layer thickness of 2.7 μm is formed on a silicon (n-Si) substrate 71 by two-step growth, and a Sample (c) has a structure in which a p-GaAs layer is formed with a layer thickness of 0.3 μm, and an N-side electrode 76 and a P-side electrode 77 are formed on both ends, and the thermal cycle layer is thermally cycled 19 times from the interface with the substrate. The other structures were fabricated in the same manner as shown in Figure 2 for each sample (d), and a p/n junction (carrier concentration p~2×10 ¹⁸ cm ^-2 , n~1×10 ¹⁷ cm ⁻³ ) The dark state current-voltage characteristics of the diode were measured. Table 2 compares the measured values of saturation current for each of the samples described above.

[Table] As is clear from Table 2, when comparing the saturation current values of each sample, the saturation current (I ₀ ) = 1 × 10 ^-8 A cm ^-2 , which is almost the same as a diode that does not undergo thermal cycling (sample c), but was created according to the present invention with a distance to the top of the thermal cycling layer of 1.9 μm. In the diode of sample (a), I ₀ = 1 × 10 ^-9 A cm ^-2 , which is about an order of magnitude lower. From this result, when using the growth layer grown according to the present invention, the It is clear that the crystallinity of the active layer formed thereon is improved. In addition, for a diode like sample (d), where the distance to the top of the thermal cycle layer was set to 1.9 μm as in sample (a) and thermal cycle growth was performed 19 times from the interface, the value of I ₀ equal to that of diode a was obtained. was gotten. From these results, it is clear that thermal cycling up to approximately 1.3 μm from the interface hardly contributes to improving crystal quality, and thermal cycling growth at a distance of more than 1.3 μm from the substrate interface in the growth direction is significant. It became clear to me that I just had to do what I was supposed to do. Thermal cycle layer (or equivalent GaAs)
The time required to form the layer) is as follows, and was approximately 170 minutes, 170 minutes, 70 minutes, and 260 minutes for samples (a) to (d) in Table 2, respectively. In other words, both samples (a) and (b) undergo 10 thermal cycles and require the same growth time, but in sample (b), the top of the thermal cycle layer has not reached a position exceeding 1.9 μm.
As mentioned above, this shows that no effect of reducing dislocations can be expected. Furthermore, as is clear from comparing samples (a) and (d), samples (a) and (d) have the same reduction effect because the upper end of the thermal cycle layer is formed at a position exceeding 1.9 μm. However, the time required varies significantly.
In other words, in the method of the present invention, until the thermal cycle layer is formed beyond 1.9 μm from the interface of the silicon substrate,
It was discovered that the formation of a thermal cycle does not contribute to the effect of reducing dislocations, and by forming a semiconductor layer that is continuously grown without a cooling cycle before forming a thermal cycle layer, the formation of a semiconductor layer can be improved. We are trying to shorten the time required for growth. In this way, by not forming a thermal cycling layer near the Si-GaAs interface and by selecting the position of the thermal cycling layer so that the top of the thermal cycling layer is at least 1.3 μm away from the interface, it is possible to shorten the thermal cycling layer. It has become possible to improve the quality of GaAs layers on silicon substrates in a time-efficient manner. Compound semiconductors formed on silicon (Si) substrates can be used as semiconductor substrates for various electronic devices and optical devices by improving their quality by reducing dislocation density using the method of the present invention. It shows excellent effects when formed to constitute a solar cell. <Effects of the Invention> As described above, according to the present invention, silicon (Si)
Compared to conventional methods, it is now possible to efficiently form a high-quality compound semiconductor single crystal layer on a substrate in a relatively short period of time, which greatly contributes to lowering the cost and weight of compound semiconductor devices. You can.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a substrate structure for explaining one embodiment of the present invention, FIG. 2 is a schematic diagram of a substrate structure for explaining another embodiment of the present invention, and FIG. 3 is a schematic diagram of a substrate structure for explaining another embodiment of the present invention. A schematic diagram of the substrate structure for explaining the compound semiconductor layer forming method, FIG. 4 is a diagram showing an example of a temperature program based on the thermal cycle growth method, and FIG. 5A
6 to 8 are schematic diagrams for explaining the reduction in dislocation density due to growth interruption and thermal cycling, and FIGS. 6 to 8 are schematic diagrams showing sample structures for comparison with the method of the present invention, respectively. 31...Silicon (Si) substrate, 32...GaAs layer,
33...GaAs thermal cycle layer, 34...GaAs layer.

Claims (1)

[Claims] 1. When growing a GaAs compound semiconductor layer on a silicon substrate, a first step of continuously growing the compound semiconductor layer without a temperature cooling cycle to form a compound semiconductor layer by the first continuous growth. Then, following the first step, by repeating the growth of the compound semiconductor layer, the interruption of the growth, and the temperature reduction during the interruption, accompanied by a temperature cooling cycle, on the compound semiconductor layer formed by the first continuous growth, a second step of sequentially growing a compound semiconductor layer conductor layer in each cycle to form a compound semiconductor layer by a second thermal cycle; The upper end of the compound semiconductor layer formed by continuous growth of step 1 and the compound semiconductor layer formed by the second thermal cycle is at least from the interface of the silicon substrate.
A method for forming a compound semiconductor layer, characterized in that it is formed at a position exceeding 1.9 μm.