JPH0548433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal generator used, for example, in testing semiconductor integrated circuits.

(Prior Art) For example, as a digital signal generator used for testing digital semiconductor integrated circuits, high level and low level can be set freely, and tri-state operation can provide high level output, low level output, and high impedance output. It is necessary to be able to obtain high-speed output, and to be able to protect the output.

FIG. 4 is a block diagram showing an example of such a conventional device. In Figure 4, V _H is a high level power supply terminal, V _L is a low level power supply terminal, and a switch circuit is connected between these power supply terminals V _H and V _L.
SWa and SWb are connected in series. Ta is an input terminal for a digital pattern signal represented by "1" and "0", and Tb is an input terminal for a control signal for controlling tri-state operation. input terminal
Ta is connected to one input terminal of the gate Ga via the inverter INV and directly connected to one input terminal of the gate Gb, and the input terminal Tb is directly connected to the other input terminal of the gate Ga and the gate Ga is connected to the other input terminal of
The output signals of these gates Ga and Gb are from a switch circuit.
This is used as the opening/closing control signal for SWa and SWb, and the output signal of gate Ga is the switch circuit.
The output signal of the gate Gb is applied to the switch circuit SWb. switch circuit
The output terminal T ₀ of the device is connected to the connection point between SWa and SWb via an output resistor R ₀ .

In such a configuration, the switch circuit SWa
When switch circuit SWa is on and SWb is off, a high level signal is output, and when switch circuit SWa is off, SWb
When is on, a low level signal is output,
When switch circuits SWa and SWb are both off, the output becomes high impedance.

(Problem to be solved by the invention) However, according to the configuration shown in FIG.
As SWa and SWb, elements with relatively high breakdown voltage and high speed must be used, resulting in high costs. Furthermore, in order to protect the output circuit, a separate protection circuit must be provided, which further increases costs.

The present invention has been made with attention to such points, and its purpose is to have a relatively simple configuration,
It is an object of the present invention to provide a low-cost digital signal generator having characteristics necessary for testing digital semiconductor integrated circuits.

(Means for Solving the Problems) The present invention achieves the above objects by using a high-level setting power supply and output current states of 0, I, and 2I.
A first current source that can take three states of output current, a second current source that can take three states of output current, 0, -I, -2I, a low level setting power supply, and an anode of the first current source.
a first diode connected to the output terminal of the current source and having its cathode connected to the output terminal of the high level setting power supply; and a first diode having its anode connected to the output terminal of the first current source and its cathode connected to the output terminal of the device. a third diode whose anode is connected to the output terminal of the device and whose cathode is connected to the output terminal of the second current source; and a third diode whose anode is connected to the low level setting power supply and whose cathode is connected to the second current source output terminal. a fourth diode connected to a current source;
In the high level state, the output current of the first current source is 2I
to set the output current of the second current source to -I, in the low level state, set the output current of the first current source to I and set the output current of the second current source to -2I, and in the high impedance state, set the output current of the first current source to -2I, , the output current of the second current source is set to zero.

(Example) Hereinafter, a detailed explanation will be given using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In Figure 1, HL is a high-level setting power supply that receives a high-level signal from the terminal _VH at DC level, and IS ₁ is a power supply with three states of 0, I, and 2I depending on the control signal applied from control circuit CL ₁ . The first current source that outputs current, _IS2 , is the second current source that outputs current in three states of 0, -I, and -2I according to the control signal applied from the control circuit _CL2 , and LL is the terminal V This is a low level setting power supply that provides a low level signal from _L at DC level. D ₁ is the anode first
A first diode whose cathode is connected to the output terminal of the current source IS ₁ and whose cathode is connected to the output terminal of the high level setting power supply HL, and D ₂ whose anode is connected to the output terminal of the first current source IS
a second diode connected to the output terminal of IS ₁ and with its cathode connected to the output terminal T ₀ of the device, D ₃ with its anode connected to the output terminal T ₀ of the device and its cathode connected to the output of the second current source IS ₂ ; the third connected to the terminal
The diode _D4 is a fourth diode whose anode is connected to the output terminal of the low level setting power supply LL and whose cathode is connected to the output terminal of the second current source _IS2 . Note that diodes D ₁ and D ₂ and
D ₃ and D ₄ each use a pair of diodes.

FIG. 2 is a circuit diagram showing a specific example of the main part of FIG. 1. The first current source IS ₁ includes transistors Q ₁ ,
The first current switch CSa consists of transistors Q ₂ and is controlled on and off by the control signal applied from the control circuit CL ₁ , and the first current switch CSa consists of transistors Q ₃ and Q ₄ and is turned on by the control signal applied from the control circuit CL ₁ . , a second current switch controlled off
It consists of CSb and cascode transistor _Q5 . On the other hand, the second current source IS ₂ includes a third current switch CSc, which is composed of transistors Q ₆ and Q ₇ and is controlled on and off by a control signal applied from the control circuit CL ₂ , and transistors Q ₈ ,
A fourth current switch CSd and a cascode transistor Q ₁₀ are configured of Q ₉ and are controlled on and off by a control signal applied from the control circuit CL ₂ .
It is made up of. In addition, each current switch
The currents Ia to Id having the same current value I are outputted from CSa to CSd, respectively.

The operation of the circuit configured in this way will be explained. FIG. 3 is an operational state diagram of the main element shown in FIG. Each of the control circuits CL ₁ and CL ₂ outputs a control signal that controls each current switch CSa to CSd to be in the on or off state as shown in FIG. 3 depending on the state of the output. When the output is at a high level, current switches CSa and CSb are turned on, so the discharge side current becomes 2I, and the current switch
Since CSc is turned off and CSd is turned on, the suction side current becomes I, and the output level is the difference between these I.
It rises due to Then, when the output level approaches _VH , diode _D1 is turned on, and the difference flows into the high level setting power supply HL via diode _D1 . When there is no load, diodes D ₁ , D ₂
The currents flowing through the diodes D ₁ and D ₂ are equal.
Since the characteristics of are the same, the output level V ₀ becomes V _H. When the output is at low level, the current switch CSa turns off and CSb turns on, so the discharge side current becomes I, and the current switch
Since CSc and CSd are turned on, the suction side current becomes 2I, and the output level decreases due to the difference I between them. And when the output level approaches V _L , diode D ₄ turns on and the difference is across diode D ₄
Output from low level setting power supply LL via.
When there is no load, the current flowing through the diodes D ₃ and D ₄ becomes equal, and since the characteristics of the diodes D ₃ and D ₄ are the same, the output level V ₀ becomes V _L , and the output level becomes V L due to the diode D ₄ . It will be clamped to _{the L} level. In the high impedance state, current switches CSa to CSd are all turned off, and the output becomes high impedance.

With this configuration, the output rise time and fall time are determined by the output capacitance C _L
It will be determined by the charging time. here,
Since the slew rate SR is determined by I/ _CL , high speed performance can be improved by increasing the output current of the current source.

Also, the output offset is determined only by the balance of the diodes, so it will be a small value. Note that due to the flow of load current, the diode
The current flowing through D ₁ and D ₄ changes and the current flows through diode D ₁ and D 4.
Although the balance between D ₂ and D ₃ and D ₄ is disrupted, these differences can be treated as a drop due to output impedance and do not pose a practical problem.

Furthermore, since no amplifier is used, good linearity can be obtained with a simple configuration.

Further, by using a cascode transistor in the output section, only two high-voltage transistors are required, and since these transistors are used with their bases connected, relatively low-speed transistors can be used. In this case, the amplitude of the output is determined only by the breakdown voltage of these output transistors, making it easy to obtain a large amplitude.

Further, by using such a cascode transistor, it is possible to use a relatively low breakdown voltage element as other elements that require high speed performance, thereby reducing costs.

Furthermore, if we focus on the output current, only I flows at most, and it essentially has a current limiter function, so the output is protected.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a low-cost digital signal generating device that has characteristics necessary for testing digital semiconductor integrated circuits with a relatively simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a circuit diagram showing a specific example of the main part of FIG. 1, FIG. 3 is an explanatory diagram of the operating state of FIG. 2, and FIG. 4 is a block diagram showing an example of a conventional device. IS ₁ , IS ₂ ... Current source, HL ... High level setting power supply, LL ... Low level setting power supply, D ₁ to _{D 4} ...
diode.

Claims (1)

[Claims] 1. A high-level setting power supply, a first current source that can take three states of output current: 0, I, and 2I, and three states of output current: -0, -I, and -2I. a second current source capable of changing the state; a low level setting power supply; a first diode having an anode connected to the output terminal of the first current source and a cathode connected to the output terminal of the high level setting power supply; a second diode connected to the output terminal of the first current source and having a cathode connected to the output terminal of the device; and a second diode having an anode connected to the output terminal of the device and a cathode connected to the output terminal of the second current source. a third diode; and a fourth diode, the anode of which is connected to the output terminal of the low level setting power supply and the cathode of which is connected to the output terminal of the second current source; output current of
2I, the output current of the second current source is -I, in the low level state the output current of the first current source is I, the output current of the second current source is -2I, and in the high impedance state, the output current of the second current source is -2I. 1. A digital signal generator characterized in that the output current of the second current source is set to zero.