JPH0550149B2 - - Google Patents
Info
- Publication number
- JPH0550149B2 JPH0550149B2 JP58086149A JP8614983A JPH0550149B2 JP H0550149 B2 JPH0550149 B2 JP H0550149B2 JP 58086149 A JP58086149 A JP 58086149A JP 8614983 A JP8614983 A JP 8614983A JP H0550149 B2 JPH0550149 B2 JP H0550149B2
- Authority
- JP
- Japan
- Prior art keywords
- junction
- electrode
- semiconductor
- electrodes
- output electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/20—Breakdown diodes, e.g. avalanche diodes
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
従来の増幅、発振、演算装置の多くはその機能
の形成のためには複雑な回路を構成する必要があ
り、又動作周波数は少数キヤリアの拡散速度に限
界があることや接合容量の存在のため制限されて
いた。本発明はこれらの欠点に対処するものであ
る。 Many of the conventional amplification, oscillation, and arithmetic devices require complex circuits to perform their functions, and the operating frequency is limited due to the limited diffusion speed of minority carriers and the presence of junction capacitance. It was restricted. The present invention addresses these shortcomings.
本発明は、半導体Ｐ・Ｎ接合に逆方向高電界を
印加し、キヤリアの雪崩現象に基づく逆方向可逆
的絶縁破壊状態において、Ｐ・Ｎ接合遷移領域内
で雪崩現象によつて生じたキヤリアが印加高電界
により加速され高エネルギー状態において負の有
効質量を有し、その走行中における印加高電界に
垂直な方向の有効質量の平均値が負となる場合、
遷移領域外であまり多くの散乱を受けず高エネル
ギー状態で負の有効質量を保つ領域では同方向に
負抵抗を生じる現象に基づく半導体装置である。 The present invention applies a reverse high electric field to a semiconductor P/N junction, and in a reverse reversible dielectric breakdown state based on an avalanche phenomenon of carriers, the carriers generated by the avalanche phenomenon in the P/N junction transition region are When it is accelerated by an applied high electric field and has a negative effective mass in a high energy state, and the average value of the effective mass in the direction perpendicular to the applied high electric field during its travel is negative,
This is a semiconductor device based on a phenomenon in which negative resistance occurs in the same direction in a region outside the transition region that does not undergo much scattering and maintains a negative effective mass in a high energy state.
以下本発明を実施例につき図面に従つて説明す
る。 The present invention will be explained below with reference to the drawings.
第１図は、本発明における半導体素子の一実施
例の構成を示す斜視図である。 FIG. 1 is a perspective view showing the structure of an embodiment of a semiconductor device according to the present invention.
図に示すように、本実施例では半導体Ｐ・Ｎ接
合はシリコン半導体Ｐ・Ｎ接合で、又は接合面は
結晶の（100）面に平行な平面にされてある。そ
して、Ｐ型半導体領域には２個の出力用の電極
４，５が設けられてあり、この２個の電極はＰ・
Ｎ接合逆方向電圧印加用の電極を兼用するように
されてある。 As shown in the figure, in this embodiment, the semiconductor P/N junction is a silicon semiconductor P/N junction, or the junction plane is a plane parallel to the (100) plane of the crystal. Two output electrodes 4 and 5 are provided in the P-type semiconductor region, and these two electrodes are connected to the P-type semiconductor region.
It is designed to also serve as an electrode for applying an N-junction reverse voltage.
更に電極４−５間には電極６が設けられてあ
り、負抵抗をより効果的に得るようにされてい
る。以上のような構成とし、接合面を均一な平面
とすることにより、また電極４−５間で効率良く
負抵抗を得ることができる。 Further, an electrode 6 is provided between the electrodes 4 and 5 to more effectively obtain negative resistance. With the above configuration and by making the bonding surface a uniform plane, negative resistance can be efficiently obtained between the electrodes 4 and 5.
第２図は、上記実施例の半導体素子を使用した
回路の一例を示す図である。図に示すようにこの
回路例は電極４−５間に有する負抵抗は２個の等
しい抵抗R1を端子８−９間に並列に接続するこ
とにより得ている。すなわち電極４−５間の負抵
抗は発振及び双安定状態等の能動的動作として端
子８−９間に出力される。 FIG. 2 is a diagram showing an example of a circuit using the semiconductor element of the above embodiment. As shown in the figure, in this circuit example, the negative resistance between electrodes 4 and 5 is obtained by connecting two equal resistances R 1 in parallel between terminals 8 and 9. That is, the negative resistance between the electrodes 4 and 5 is output between the terminals 8 and 9 as active operation such as oscillation and bistable state.
第３図は、端子８−９間に存在する負抵抗−
R1とその負抵抗に並列に存在する正抵抗RPとの
関係を示す図であり、両抵抗の大きさによる動作
の変化は以下に示すようになる。 Figure 3 shows the negative resistance present between terminals 8 and 9.
This is a diagram showing the relationship between R 1 and a positive resistance R P existing in parallel with the negative resistance, and changes in operation depending on the magnitude of both resistances are as shown below.
Ｐ−Ｎ接合における雪崩現象によつて生じた電
流Ｉが増加するに従い負抵抗−RNの絶対値RNは
減少する。そして正抵抗RPと同じ値（RN＝RP）
になつたとき端子８−９間に双安定状態が生じ、
端子８及び９の電圧は互いに極性が正又は負の値
をとることのできる状態になる。なお、この状態
においては、例えば第４図に示すように電極４−
５間に制御用の電極１２，１３を設けることによ
り双安定装置として使用することができる。 As the current I generated by the avalanche phenomenon at the PN junction increases, the absolute value R N of the negative resistance -R N decreases. And the same value as the positive resistance R P (R N = R P )
When , a bistable state occurs between terminals 8 and 9,
The voltages at terminals 8 and 9 are in a state where their polarities can take positive or negative values. In this state, for example, as shown in FIG.
By providing control electrodes 12 and 13 between 5, it can be used as a bistable device.
更に電流Ｉが増加すると、負抵抗−RNの絶対
値RNは正抵抗RPより小さくなり（RN＜RP）、端
子８−９間で発振可能な状態となる。この状態に
おいては、端子８−９間にキヤパシタンス手段お
よびインダクタンス手段を直列に接続することに
より発振装置として使用することができる。 When the current I further increases, the absolute value R N of the negative resistance -R N becomes smaller than the positive resistance R P (R N <R P ), and a state becomes possible where oscillation is possible between the terminals 8 and 9. In this state, by connecting capacitance means and inductance means in series between terminals 8 and 9, it can be used as an oscillation device.
上記実施例において、Ｅ＝7.8Vで雪崩現象が
開始される試料について、R1＝1KΩ、R2＝300
ΩのときＥ＝11.8V、Ｉ＝5.3ｍＡで双安定状態が
開始され、双安定状態における端子８−９間の電
圧はＥの増加に伴つて1.0Vから1.7Vまで、端子
８−９を短絡したときの電流は2.5ｍＡから4.4ｍ
Ａまで増加した。更にＥ＝13.7V、Ｉ＝10.8ｍＡ
で発振状態が生じ、発振出力約20ｍＷ、効率約10
％、最高発振周波数的250MHzが得られた。 In the above example, for the sample where the avalanche phenomenon starts at E = 7.8V, R 1 = 1KΩ, R 2 = 300
When Ω, a bistable state starts at E=11.8V and I=5.3mA, and the voltage between terminals 8-9 in the bistable state increases from 1.0V to 1.7V as E increases. The current when short-circuited is 2.5mA to 4.4m
It increased to A. Furthermore, E=13.7V, I=10.8mA
An oscillation state occurs, with an oscillation output of about 20 mW and an efficiency of about 10
%, the highest oscillation frequency of 250MHz was obtained.
以上に述べたように本発明によると、出力端子
で得られる負抵抗は雪崩現象により発生したキヤ
リアの負有効質量に基づいているため、従来より
簡単な回路で、しかも高速の動作の可能な双安定
装置、および発振装置等の能動的装置を構成する
ことができる。 As described above, according to the present invention, the negative resistance obtained at the output terminal is based on the negative effective mass of the carrier generated by the avalanche phenomenon. Active devices such as stabilizers and oscillators can be configured.
第１図は、本発明の一実施例の斜視図、第２図
は本実施例を使用した回路の一例を示す図、第３
図は負抵抗と正抵抗の関係を示す図、第４図は本
発明に基づく双安定装置の一例を示す図である。
１……Ｐ型半導体部分、２……Ｎ型半導体部
分、３……Ｐ・Ｎ接合遷移領域、４，５，６，
７，１２，１３……電極、８，９，１０，１１，
１４，１５……端子、Ｅ……電源、R1，R2，R3，
RN，RP……抵抗。
Fig. 1 is a perspective view of an embodiment of the present invention, Fig. 2 is a diagram showing an example of a circuit using this embodiment, and Fig. 3 is a perspective view of an embodiment of the present invention.
The figure is a diagram showing the relationship between negative resistance and positive resistance, and FIG. 4 is a diagram showing an example of a bistable device based on the present invention. 1... P-type semiconductor part, 2... N-type semiconductor part, 3... P/N junction transition region, 4, 5, 6,
7, 12, 13... Electrode, 8, 9, 10, 11,
14, 15... terminal, E... power supply, R 1 , R 2 , R 3 ,
R N , R P ...resistance.
Claims (1)
形成するＰ型半導体領域およびＮ型半導体領域の
うちいずれか一方の領域に２個の出力およびＰ・
Ｎ接合逆方向電圧印加兼用の電極を設け、前記２
個の出力用の電極を設けた領域に対するもう一方
の領域に１個のＰ・Ｎ接合逆方向電圧印加用の電
極を設けた半導体素子と、前記各２個の出力用の
電極に各々その一端が接続された２個の抵抗手段
と、前記各２個の抵抗手段の共通の他の一端と前
記１個の電極間に接続され、前記Ｐ・Ｎ接合に逆
方向雪崩破壊電圧を印加する電源を設けた、キヤ
リアの雪崩現象に基づくＰ・Ｎ接合逆方向可逆的
絶縁破壊状態において、前記２個の出力用の電極
間にキヤリアの負有効質量に基づく負抵抗を有す
ることを特徴とする半導体装置。 ２ 前記２個の出力用の電極間に２個の入力用の
電極を設け、Ｐ・Ｎ接合逆方向可逆的絶縁破壊状
態において、前記２個の入力用の電極間に入力す
る制御信号により制御された前記負抵抗に基づく
双安定出力を前記２個の出力用の電極間に得るこ
とを特徴とする特許請求の範囲１記載の半導体装
置。 ３ 前記２個の出力用の電極間に１個のＰ・Ｎ接
合逆方向電圧印加用の電極を設け、この１個の
Ｐ・Ｎ接合逆方向電圧印加用の電極および前記電
源間に１個の抵抗手段を接続した特許請求の範囲
１又は２記載の半導体装置。[Scope of Claims] 1. A semiconductor device having a semiconductor P/N junction, and having two outputs and a P/N junction in either one of the P-type semiconductor region and the N-type semiconductor region forming the P/N junction.
An electrode that also serves as an N-junction reverse voltage application is provided, and the above-mentioned 2
A semiconductor element having one P/N junction electrode for applying a reverse voltage in the other region to the region provided with the two output electrodes, and one end of each of the two output electrodes. two resistance means connected to each other, and a power source connected between the other common end of each of the two resistance means and the one electrode, and applying a reverse avalanche breakdown voltage to the P/N junction. A semiconductor having a negative resistance based on the negative effective mass of the carrier between the two output electrodes in a P/N junction reverse reversible dielectric breakdown state based on the avalanche phenomenon of the carrier. Device. 2. Two input electrodes are provided between the two output electrodes, and control is performed by a control signal input between the two input electrodes in a P/N junction reverse reversible dielectric breakdown state. 2. The semiconductor device according to claim 1, wherein a bistable output based on said negative resistance is obtained between said two output electrodes. 3. One P/N junction reverse voltage application electrode is provided between the two output electrodes, and one P/N junction reverse voltage application electrode is provided between this one P/N junction reverse voltage application electrode and the power source. 3. The semiconductor device according to claim 1, further comprising a resistor connected to the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58086149A JPS59211284A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58086149A JPS59211284A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59211284A JPS59211284A (en) | 1984-11-30 |
| JPH0550149B2 true JPH0550149B2 (en) | 1993-07-28 |
Family
ID=13878678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58086149A Granted JPS59211284A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59211284A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229636A (en) * | 1987-09-01 | 1993-07-20 | Tatsuji Masuda | Negative effective mass semiconductor device and circuit |
| JP3284491B2 (en) | 1997-07-08 | 2002-05-20 | 達治 増田 | SR flip flop |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147307B2 (en) * | 1971-09-07 | 1976-12-14 |
-
1983
- 1983-05-16 JP JP58086149A patent/JPS59211284A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59211284A (en) | 1984-11-30 |
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