JPH0566772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit that determines whether two sets of data, each consisting of n bits, match.

(Prior art) Figure 1 is a logic diagram of an 8-bit data match determination circuit. A signal indicating whether or not the data match is output. Conventional circuits of this type were constructed of a combination of eight exclusive OR gates and an eight-input OR gate, or a combination of eight exclusive OR gates and an eight-input NAND gate.
The circuit shown in Figure 2 is known as an exclusive NOR gate using field effect transistors.
If a data match determination circuit is constructed using this gate, the circuit shown in FIG. 3 will be obtained. In this way, conventional circuits require multi-input NAND gates, so
If you try to increase the data width while keeping the logic threshold and drive capacity of a multi-input gate constant, a transistor with a large drive capacity will be required for the field effect transistor in the multi-input gate. There was a problem of an increase in the number of people (such as In particular, when the data width is increased from 8 bits to 16 bits or from 16 bits to 32 bits, the amount of hardware increases in the conventional data match determination circuit, making it unsuitable for LSI implementation. For this reason, there has been a desire for a data match determination circuit that requires less metal and is suitable for LSI implementation.

(Object of the invention) The present invention is characterized in that it is configured with an exclusive OR circuit that can be wired and has a small number of elements.
The purpose is to provide a data match determination circuit that has a small amount of hardware and is suitable for LSI implementation as a circuit for determining whether two sets of data having a wide data width match or do not match.

(Structure of the Invention) In order to achieve the above object, the present invention provides a first connection portion connecting a source terminal of a first field effect transistor and a gate terminal of a second field effect transistor, and a gate terminal of the first field effect transistor. and second
A unit obtained by connecting each drain terminal of the pair of field effect transistors to a cathode terminal of a diode, in which each of the second connection parts connected to the source terminals of the field effect transistors is an input terminal for two data to be determined. n circuits are provided, the anode terminals of the n diodes are connected to one terminal of a load element, the other terminal of the load element is connected to a power supply, and a connection part between the n diodes and the load element is provided. The gist of the invention is a data match determination circuit characterized in that the output terminal is .

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

FIG. 4 shows an embodiment of the present invention,
This is an example of a circuit that identifies whether two sets of 2-bit data match or do not match. In the figure, Q1 to Q6 are field effect transistors, 1 is a load element, 2 is an output terminal, and 3
is a field effect transistor Q1. Connection point of Q2 and Q3, 4 is field effect transistor Q4, Q5, Q6
, 5 to 8 are data input terminals, and 9 is a unit circuit. This circuit is composed of two unit circuits 9 and a load element 1, and each unit circuit 9 is connected to field effect transistors Q2 and Q3 (or field effect transistors Q5 and Q6) for data comparison in order to enable wired connection. It is composed of an additional field effect transistor Q1 (or field effect transistor Q4).

For example, to explain one configuration of the unit circuit 9, the source of the field effect transistor Q2 is connected to the first
, the source of the field effect transistor Q3 is the second input terminal 6, the drains of the field effect transistors Q2 and Q3 are connected to each other, and the source of the field effect transistor Q1 is connected to this connection point 3. And this field effect transistor Q1
The drain of the field effect transistor Q2 is connected to the output terminal 2, the gate of the field effect transistor Q2 is connected to the input terminal 6, and the gate of the field effect transistor Q3 is connected to the input terminal 5. Also, field effect transistor Q
1 is connected to an output terminal 2.

Next, the operation will be explained.

In order to compare two sets of data, D1, D0 and D1', D0', input D0 to data input terminal 5, D0' to data input terminal 6, D1 to data input terminal 7, and D1' to data input terminal 8. do. When input data D0, D0' are both at low level, field effect transistors Q2, Q3 are in a cut-off state.
When input data D0 and D0' are both high level,
Although the connection point 3 rises to a high level, even if the output terminal 2 is at a low level, no current flows from the connection point 3 to the output terminal 2 because of the field effect transistor Q1. Therefore, a phenomenon in which the potential of the output terminal 2 increases due to current flowing into other input terminals via the output terminal 2 does not occur. Further, when one of the input data D0 and D0' is at a high level and the other is at a low level, either field effect transistor Q2 or Q3 is turned on. for example,
When input data D0 is low level, input data D0'
is at a high level, the field effect transistor Q2
turns on, current flows through the field effect transistor Q2 to the data input terminal 5 to lower the potential at the connection point 3 to a low level, and lowers the potential at the output terminal 2 to a low level. The unit circuit 9 composed of field effect transistors Q4, Q5, and Q6 also operates in a similar manner. Therefore, input data D0 and D
0', at least one of the input data D1 and D1'
When the pairs do not match, a current flows to the input terminal whose input data is at a low level, and the output terminal 2 becomes at a low level. On the other hand, when all the sets of input data D0 and D0' and input data D1 and D1' match, the output terminal 2 becomes high level.

Although the above explanation has been given to a data match determination circuit for 2-bit data, a data match determination circuit for n-bit data can generally be realized by using n unit circuits 9. Figure 5 shows an example in which this circuit is applied to an 8-bit data match judgment circuit, and even if a buffer circuit is added, it can be configured with 29 elements.
The wiring is also simple and can be realized with a small amount of hardware.
On the other hand, in the case of the conventional data match judgment circuit shown in Fig. 3, wiring is complicated due to the connection of the exclusive NOR gate and the multi-input gate, which requires 33 elements. A large amount of metal is required due to the fact that the field effect transistor requires a transistor with a large driving ability.

(Effects of the Invention) As explained above, according to the present invention, irrespective of the data width to be determined, by adding the unit circuit 9 consisting of three field effect transistors, it is possible to determine the coincidence of n-bit data. can be done,
A data match determination circuit for n-bit data can be realized with a simple circuit configuration that requires a small amount of metal materials. Therefore, even when n is large, this data matching judgment circuit can be implemented with a small amount of metal, and high density is required.
It has an effect that is suitable as an LSI circuit.

[Brief explanation of drawings]

FIG. 1 is a logic diagram of a data match determination circuit, FIG. 2 is an exclusive NOR gate, FIG. 3 is a data match determination circuit according to the prior art, FIG. 4 is a data match determination circuit according to the present invention, and FIG. 5 This is an example in which the present invention is applied to a match determination circuit for 8-bit data. D0-D7...Input data I, D0'-D7'...
...Input data, Q1-Q6...Field effect transistor, 1...Load element, 2...Output terminal, 3...
...Connection point of field effect transistors Q1, Q2, Q3, 4...Field effect transistors Q4, Q5, Q
6 connection points, 5 to 8...data input terminals, 9...
unit circuit.

Claims (1)

[Claims] 1 A first connection portion connecting the source terminal of the first field effect transistor and the gate terminal of the second field effect transistor; and a second connection portion connecting the gate terminal of the first field effect transistor and the source terminal of the second field effect transistor. n unit circuits are provided by connecting each drain terminal of the pair of field effect transistors to a cathode terminal of a diode, each of the connection portions of which are input terminals for the two data to be determined, and each of the n diodes data characterized in that an anode terminal of the load element is connected to one terminal of a load element, the other terminal of the load element is connected to a power source, and a connection portion between the n diodes and the load element is an output terminal. Matching judgment circuit.