JPH056930B2 - - Google Patents
Info
- Publication number
- JPH056930B2 JPH056930B2 JP61236541A JP23654186A JPH056930B2 JP H056930 B2 JPH056930 B2 JP H056930B2 JP 61236541 A JP61236541 A JP 61236541A JP 23654186 A JP23654186 A JP 23654186A JP H056930 B2 JPH056930 B2 JP H056930B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminal
- electrode
- current
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に入力ゲート保
護回路を有する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an input gate protection circuit.
GaAs半導体は、Siに比べ電子の移動度が数倍
速く、さらに半絶縁性基板を容易に得ることが出
来るため、集積化を図る際に配線−基板間の容量
を低減出来、高速論理動作が可能である。現在、
GaAs素子の集積化はシヨツトキー接合を用いた
MESFETが主流であり、量産化を目指して各所
で精力的な研究がなされているが、
GaAsMESFETのゲートは、静電気などによる
サージが加わつた場合、容易に破壊してしまう欠
点がある。このため従来第２図に示すような入力
保護回路が考えられていた。すなわち、入力端子
１０から抵抗２０を介して電源端子１５から電位
を供給されたシヨツトキーダイオード５，６が接
続され、この接続点が半導体素子の入力端となつ
ている。この回路は、入力端子１０に加わつたサ
ージ電圧の影響を抵抗２０により電流を制限し、
又シヨツトキーダイオード５，６からは電位を決
定し、MESFETのゲートに大電流や大電圧が加
わらないように働いている。
GaAs semiconductors have electron mobility several times faster than Si, and semi-insulating substrates can be easily obtained, so the capacitance between wiring and substrate can be reduced when integrating, allowing high-speed logic operation. It is possible. the current,
GaAs devices are integrated using Schottky junctions.
MESFET is the mainstream, and vigorous research is being carried out in various places with the aim of mass production.
The disadvantage of GaAs MESFET gates is that they are easily destroyed by surges caused by static electricity. For this reason, an input protection circuit as shown in FIG. 2 has been conventionally considered. That is, Schottky diodes 5 and 6 to which a potential is supplied from a power supply terminal 15 via a resistor 20 are connected to an input terminal 10, and this connection point serves as an input end of the semiconductor element. This circuit limits the current by resistor 20 to suppress the influence of surge voltage applied to input terminal 10.
The Schottky diodes 5 and 6 also determine the potential and work to prevent large currents and voltages from being applied to the gate of the MESFET.
しかしながら、第２図に示す保護回路でサージ
にして効果を得ようとすると、抵抗２０の抵抗値
に高抵抗が必要となり、現在のイオン注入による
抵抗の形成方法では、非常に大きな面積になる
か、又は面積を小さく抑えるためにイオン注入の
ドーズ量を減らすと、そのためにGaAs特有の表
面準位の影響によつて得られる再現性の悪い抵抗
を用いるしかなかつた。
However, if the protection circuit shown in Figure 2 is to be used to generate an effect from surges, the resistance value of the resistor 20 will need to be high, and the current method of forming a resistor by ion implantation will require a very large area. Or, if the dose of ion implantation is reduced in order to keep the area small, there is no choice but to use a resistance with poor reproducibility obtained due to the influence of surface states specific to GaAs.
本発明の目的は、入力ゲートをサージから保護
し、かつ保護のためにチツプ面積を増大させない
保護回路をもつ半導体装置を提供することにあ
る。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a protection circuit that protects an input gate from surges and does not increase the chip area for protection.
本発明の半導体装置は、コレクタ電極が入力端
子に接続されエミツタ電極が出力端子として入力
端となりベース電極が適当にバイアスされたバイ
アス回路に接続されたバイポーラトランジスタ
と、一端が前記出力端子と接続され他端が電源端
子と接続され互にアノード電極とカーソド電極が
逆極性に並列接続された２個のダイオードからな
る回路とを有する入力保護回路を備えることを特
徴とする。
The semiconductor device of the present invention includes a bipolar transistor having a collector electrode connected to an input terminal, an emitter electrode serving as an input terminal, and a base electrode connected to an appropriately biased bias circuit, and one end connected to the output terminal. The input protection circuit is characterized in that it includes a circuit consisting of two diodes whose other ends are connected to a power supply terminal and whose anode electrodes and cathode electrodes are connected in parallel with opposite polarities.
本発明の半導体装置構成によれば、入力に正の
サージが加わつた場合カソード電極が電源に接続
されたダイオードにより入力から電源に向かつて
電流が流れ、その電流の大きさはトランジスタの
ベース電流で決定される。また、負のサージが入
つた場合にはアノード電極が電源に接続されたダ
イオードにより電源から入力に向かつて電流が流
れ、MESFETのゲートに負の過電圧が印加しな
いように働きFETのゲートを保護する。この時
の電流値もトランジスタのコレクタ電極とエミツ
タ電極を入れ替えて考えることで正のサージが印
加した時の電流がわかる。
According to the semiconductor device configuration of the present invention, when a positive surge is applied to the input, a current flows from the input toward the power source due to the diode whose cathode electrode is connected to the power source, and the magnitude of the current is determined by the base current of the transistor. It is determined. In addition, when a negative surge occurs, a diode whose anode electrode is connected to the power supply causes a current to flow from the power supply to the input, which protects the FET gate by preventing negative overvoltage from being applied to the MESFET gate. . The current value at this time can also be determined by swapping the collector and emitter electrodes of the transistor to determine the current when a positive surge is applied.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図に本発明の一実施例の回路図である。バ
イポーラトランジスタ１はベース電極が抵抗２，
３により一定の電流が流れるようにバイアスさ
れ、コレクタ電極が入力端子１０に接続され、エ
ミツタ電極が出力端子１１に接続されている。こ
のバイポーラトランジスタ１のベース電極にバイ
アスを供給する回路は、電源端子１６，１７の間
に接続された抵抗２，３によつて調整することが
できる。シヨツトキー接合ダイオード５はアノー
ド電極が電源の端子１５に接続され、カソード電
極が出力端子１１に接続され、シヨツトキー接合
ダイオード６はアノード電極が出力端子１５に接
続されカソード電極が電源の端子１１に接続され
ている。いま、入力端子１０にサージが入力した
とすると、正のサージに対しては、ダイオード６
により入力から電源に電流が流れ、負のサージに
対しては、ダイオード５により電源から入力に電
流が流れる。ここで、バイポーラトランジスタ１
はダイオードに流れる電流を制限する働きを持
つ。 FIG. 1 is a circuit diagram of an embodiment of the present invention. The base electrode of the bipolar transistor 1 is a resistor 2,
3 so that a constant current flows, the collector electrode is connected to the input terminal 10, and the emitter electrode is connected to the output terminal 11. A circuit for supplying bias to the base electrode of bipolar transistor 1 can be adjusted by resistors 2 and 3 connected between power supply terminals 16 and 17. The Schottky junction diode 5 has its anode electrode connected to the terminal 15 of the power source and its cathode electrode connected to the output terminal 11, and the Schottky junction diode 6 has its anode electrode connected to the output terminal 15 and its cathode electrode connected to the terminal 11 of the power source. ing. Now, if a surge is input to the input terminal 10, the diode 6 will be connected to the positive surge.
Therefore, current flows from the input to the power supply, and in response to a negative surge, current flows from the power supply to the input due to the diode 5. Here, bipolar transistor 1
has the function of limiting the current flowing through the diode.
以上説明したように、本発明による半導体装置
は入力に入つたサージ電圧をバイポーラトランジ
スタ１とシヨツトキー接合ダイオード５，６によ
り充放電させてFETの入力を保護する効果を持
ち、さらにこのゲート保護のための素子が大きく
なることはない。このような入力保護回路は、
GaAsLSIにおいて大負荷を駆動する際にバイポ
ーラトランジスタを用いることにより、
MESFETを用いてSi半導体のBi−CMOSに相当
する回路を構成する入力保護の目的で新たに別の
素子を作製する必要がないため効力を発揮する。
As explained above, the semiconductor device according to the present invention has the effect of protecting the input of the FET by charging and discharging the surge voltage that enters the input through the bipolar transistor 1 and the Schottky junction diodes 5 and 6, and further has the effect of protecting the input of the FET. The elements will not become larger. Such an input protection circuit is
By using bipolar transistors when driving large loads in GaAsLSI,
This is effective because there is no need to create a separate element for the purpose of input protection, which uses MESFET to configure a circuit equivalent to Bi-CMOS of Si semiconductors.
第１図は本発明の一実施例を説明するための回
路図、第２図は従来技術を説明するための回路図
である。
１……バイポーラトランジスタ、５，６……シ
ヨツトキー接合ダイオード、２，３，２０……抵
抗、１０……入力端子、１１……出力端子、１
５，１６，１７……電源端子、１８……節点。
FIG. 1 is a circuit diagram for explaining an embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining a conventional technique. 1... Bipolar transistor, 5, 6... Schottky junction diode, 2, 3, 20... Resistor, 10... Input terminal, 11... Output terminal, 1
5, 16, 17...power terminal, 18...node.
Claims (1)
電極が出力端子として入力端となりベース電極が
適当にバイアスされたバイアス回路に接続された
バイポーラトランジスタと、一端が前記出力端子
と接続され他端が電源端子と接続され互にアーノ
ド電極とカソード電極とが逆極性に並列接続され
た２個のダイオードからなる回路とを有する入力
保護回路を備えることを特徴とする半導体装置。1 A bipolar transistor with a collector electrode connected to an input terminal, an emitter electrode as an output terminal, an input terminal, and a base electrode connected to an appropriately biased bias circuit, one end connected to the output terminal and the other end as a power supply terminal. 1. A semiconductor device comprising an input protection circuit comprising two diodes connected in parallel with an anode electrode and a cathode electrode of opposite polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61236541A JPS6390208A (en) | 1986-10-03 | 1986-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61236541A JPS6390208A (en) | 1986-10-03 | 1986-10-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6390208A JPS6390208A (en) | 1988-04-21 |
| JPH056930B2 true JPH056930B2 (en) | 1993-01-27 |
Family
ID=17002196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61236541A Granted JPS6390208A (en) | 1986-10-03 | 1986-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390208A (en) |
-
1986
- 1986-10-03 JP JP61236541A patent/JPS6390208A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6390208A (en) | 1988-04-21 |
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