JPH0572770B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device.
The present invention relates to an integrated circuit device having a built-in (Integrated Injection Logic) type logic circuit that can reduce delay in an input circuit section without increasing current consumption.

[Prior art]

An example of a conventional integrated circuit device is shown in Fig. 1. In the figure, R ₁ and R ₂ are resistors, and T ₁ is an NPN.
The transistors form the input circuit section, and the PNP transistor T ₂ and NPN transistor T ₃ form the basic gate of the IIL type logic circuit section. V ₁ is an input signal, and V ₂ is an output signal of the input circuit section and an input signal of the IIL type logic circuit section. Further, G is the GND/G terminal (ground) of the circuit.

And the collector of NPN transistor T ₁ is
connected to the collector of PNP transistor T ₂ and to the base of NPN transistor T ₃ ;
The emitter of NPN transistor _T1 is
It is connected to the GND/G terminal, and its base is connected via a resistor R ₁ to an input terminal to which an input signal V ₁ is applied, and is also connected to the GND/G terminal of the circuit via a resistor R ₂ . Also, PNP transistor _T2
The emitter is connected to the power supply terminal, and the base is connected to the GND/G terminal of the circuit. Also, NPN
The collector of the transistor _T3 is formed into a multi-collector, and its emitter is connected to the GND/G terminal of the circuit.

The operation of the circuit configured in this way will be explained with reference to FIG.

First, the input threshold voltage of the IIL logic circuit is NPN
This is the forward voltage drop (V _BE ) between the base and emitter of transistor T ₃ and is usually around 0.6 to 0.8 ^V. Since this input threshold voltage is low, it is necessary to apply an input voltage of about 0.4 ^V or less to provide the "L" level of the logic input level. For this reason, the NPN transistor _T1 is normally operated in saturation.

Next, Figure 2 shows the input/output delay time characteristics of the input circuit section when the NPN transistor T ₁ operates in saturation, and the delay times t _ON , t _S ,
Of t _F , the delay time t _S gives a particularly large delay time, and this is because excessive minority carriers are accumulated in the base region and collector region of the NPN transistor T ₁ when the NPN transistor T ₁ is saturated. .

Under the condition that the "L" level output voltage is 0.4 ^V or less, an NPN transistor is used as a means to reduce the accumulation delay time _tS .
To prevent deep saturation between the base and collector of _T1 , there is a way to clamp it with a shot key barrier diode (SBD).

However, such means is not practical in manufacturing integrated circuits because it requires additional special adjustments and processes.

[Summary of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to provide a simple structure for connecting an IIL type integrated circuit section and an input circuit. An object of the present invention is to provide an integrated circuit device that can reduce delays in an input circuit and is suitable when high-speed operation is required.

In order to achieve such an object, the present invention provides a means of inserting a diode to connect the IIL type logic circuit section to the GND level potential of the IIL type logic circuit section when coupling the IIL type logic circuit section and the input circuit section in an integrated circuit. to increase the apparent input threshold voltage to V _BE +V _F
(However, V _F indicates the forward voltage drop of the diode inserted between the IIL GND and the system GND.) By setting this, the circuit configuration of the input circuit section can be made into a non-saturated type circuit. It is designed to improve the operation delay caused by the saturation delay time (t _S ).

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a circuit diagram showing an embodiment of an integrated circuit device according to the present invention.

In Fig. 3, the same numbers as in Fig. 1 indicate corresponding parts, R ₁₁ and R ₁₂ are resistors, and T ₁₁ is NPN.
The transistors D ₁ and D ₂ are diodes, which constitute the input circuit section. Then, as in FIG. 1, the PNP transistor T ₂ of FIG.
PNP transistor T ₁₂ corresponding to
The IIL logic circuit section is composed of NPN transistor _T13 , which corresponds to NPN transistor _T3 .
The base of the PNP transistor _T12 and the emitter of the NPN transistor _T13 are connected, and the connection point is connected to the circuit's GND and GND through the diode _D3 in the forward direction.
connected to the terminal.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4. FIG. 4 shows the delay time characteristics of the input circuit section in the embodiment shown in FIG.

First, since a diode _D3 is inserted between the emitter of the NPN transistor _T13 and the GND/G terminal of the circuit, the input threshold voltage (V _TH ) of the NPN transistor _T13 is shown in Figure 1. Forward voltage drop of diode _D3 compared to the circuit (V _F )
It has been lifted by that amount.

Next, in the input circuit section of FIG. 3, the "L" level of the collector voltage (V _O ) of the NPN transistor T ₁₁ is clamped by the diode D ₂ to approximately 0.7V.
However, since the input threshold voltage of the NPN transistor _T13 is about 1.4 ^V , it is “L”.
The voltage level is sufficient.

And in this circuit, NPN transistor
Since T ₁₁ does not operate in saturation, the delay time t _S can be regarded as 0, as shown in the operating waveform of FIG. 4, and the operation delay in the input circuit section can be improved.

〔Effect of the invention〕

As is clear from the above description, the present invention has a simple circuit configuration in which the GND level of the entire IIL logic circuit is raised so that a non-saturated input circuit format can be used without using complicated means. Therefore, when the IIL logic circuit section and the input circuit section are coupled, the delay in the input circuit can be reduced, which is extremely effective when high-speed operation is required.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional integrated circuit device, FIG. 2 is an operation waveform diagram showing delay time characteristics of the input circuit section to explain the operation of FIG. 1, and FIG. 3 is an integrated circuit according to the present invention. FIG. 4 is a circuit diagram showing one embodiment of the device, and FIG. 4 is an operation waveform diagram showing delay time characteristics of the input circuit section to explain the operation of FIG. 3. T ₁₁ , T ₁₃ ...NPN transistor, T ₁₂ ...
PNP transistor, _R11 , _R12 ...Resistance, _D1 to _D3
……diode.

Claims (1)

[Claims] 1 a first diode element whose anode is connected to an input node to which an input signal is supplied; a second diode element whose anode is connected to the input node; and a base connected to the cathode of the first diode element. The first diode element operates in a non-saturation region with its collector connected to the cathode of the second diode element and its emitter connected to the ground node.
an input circuit section having an NPN transistor; a PNP transistor having an emitter connected to a power supply potential node and a collector connected to the collector of the first NPN transistor; a base connected to the collector of the first NPN transistor; a second NPN transistor having an emitter connected to the base of the PNP transistor; An integrated circuit device equipped with a diode element for raising the emitter potential of a transistor from ground potential.