JPH0583191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a manufacturing method that facilitates _hFE control of an NPN transistor in a semiconductor integrated circuit incorporating an MIS type capacitive element.

(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are essential steps, as well as the high-concentration buried layer formation step and epitaxial layer growth step to reduce the collector series resistance.
This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for junction isolation of each element and the electrode formation process for electrical connection.

On the other hand, due to circuit requirements, other elements, such as
There is a demand for incorporating a PNP transistor, resistor, capacitor, and Zener diode on the same board.
In this case, it goes without saying that it is preferable to utilize the basic steps as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration being given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, a new process may be added not for the purpose of forming a basic NPN transistor, but for the purpose of incorporating other elements or improving the characteristics of other elements. For example, a P ⁺ diffusion step for forming an anode region that controls the Zener voltage of the Zener diode with the cathode region by the emitter diffusion;
R diffusion process and implant resistance formation process to form a resistance region with a different resistivity from the base region,
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the MOS type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN transistors, all of which are suitable for bipolar IC applications and This is a step (optional step) in which it is decided whether or not to add it after consideration from the viewpoint of purpose and cost.

FIG. 4 shows an MIS type capacitor formed using the above optional process. In the figure, 1 is a P type semiconductor substrate, 2 is an N type epitaxial layer, 3 is an N ⁺ type buried layer, 4 is a P ⁺ type isolation region, 5 is an island,
6 is the N ⁺ lower electrode region by emitter diffusion, 7 is a silicon nitride film (Si ₃ N ₄ ) as a high dielectric insulator,
8 is an upper electrode made of aluminum material, 9 is an oxide film, and 10 is an electrode. In addition, using a nitride film
The MIS type capacitor is described in, for example, Jikai Publication No. 60-244056.

(c) Problems to be solved by the invention However, since the conventional MIS type capacitor uses the emitter diffusion process of an NPN transistor as the lower electrode, a nitride film is formed after depositing the N-type impurity to form the emitter region. After that, drive-in of N-type impurities must be performed. Then, because the heat treatment at around 800℃ used for nitride film deposition diffuses the emitter region, the h _FE (current amplification factor) of the NPN transistor varies greatly.
The drawback was that it was difficult to control.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not the optional process necessary for forming the nitride film is added, so process management is required for each model, which has the disadvantage that management cannot be standardized. Ta.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned drawbacks.
In the method of manufacturing a semiconductor integrated circuit incorporating a type capacitor, boron B is removed from the surface of the epitaxial layer 23.
The isolation region 24 and the lower electrode region 26 are formed by selectively diffusing the lower electrode region 26.
In addition to being used as the lower electrode of the MIS type region, a nitride film (Si ₃ N4 ₄ ) is deposited on the surface of the lower electrode region 26 to form a dielectric thin film 29 for MIS type capacitance.
It is characterized by emitter diffusion of an NPN transistor.

(E) Effect According to the present invention, since the lower electrode region 26 formed using the diffusion process of the isolation region 24 is used as the lower electrode of the MIS type capacitor, the nitride film is deposited before the emitter diffusion process. This makes it possible to eliminate heat treatment that would cause variations in the h _FE of the NPN transistor after the emitter region 30 is formed.

(F) Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor integrated circuit according to the present invention, in which 21 is a P-type silicon substrate, 22 is a substrate 2
23 is an N ^- type epitaxial layer laminated on the entire surface of the substrate 21, and 24 is a P ⁺ -type isolation region penetrating the epitaxial layer 23. , 25 is an island in which the epitaxial layer 23 is formed in the form of an island by the isolation region 24, and 26 is an island in which the epitaxial layer 23 is simultaneously formed on the surface of one island 25 using the diffusion process of the isolation region 24. The lower electrode region of the P ⁺ type MIS type capacitor reaching up to the layer 22, 27 is the P-type base region of the NPN transistor formed on the surface of the other island 25, and 28 is the silicon oxide film (SiO ₂ ) covering the surface of the epitaxial layer 23. ), 29
3 is the dielectric film of the MIS type capacitor deposited on the surface of the lower electrode region 26; 30 is the N ⁺ type emitter region of the NPN transistor formed on the surface of the base region 27;
1 is an N ⁺ type collector contact region for taking out the collector of the NPN transistor formed on the surface of the island 25; 32 is an electrode made of aluminum material that is in ohmic contact with each region through a contact hole; 33 is an electrode of the dielectric thin film 29; This is an upper electrode provided above so as to face the lower electrode region 26 . The entire bottom of the lower electrode region 26 is formed so as to be in contact with the buried layer 22, and the lower electrode region 26 is electrically insulated from the ground potential of the substrate 21 by the buried layer 22. Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration.

According to the structure of the present application described above, since the lower electrode region 26 formed at the same time as the isolation region 24 is used as the lower electrode of the MIS type capacitor, the step of forming the dielectric thin film 29 is arranged before the emitter diffusion step. be able to.

Below, the manufacturing method of the present application is shown in FIGS. 2A to 2F.
Explain using.

First, as shown in FIG. 2A, the surface of a P-type silicon semiconductor substrate 21 is selectively doped with N-type impurities such as antimony (Sb) or arsenic (As) to form N ⁺
A mold embedding layer 22 is formed to a thickness of 5 to 50% over the entire surface of the substrate 21.
A 10μ N-type epitaxial layer 23 is laminated.

Next, as shown in FIG. 2B, boron B is selectively diffused from the surface of the substrate 21 to form P ⁺ type isolation regions penetrating the epitaxial layer 23 so as to surround the buried layers 22 respectively. Form 24. The epitaxial layer 23 surrounded by the isolation region 24 becomes an island 25 for forming each circuit element. At the same time, boron B in the isolation region 24 diffusion process
is also diffused into a region corresponding to the buried layer 22 on the surface of the island 25 to form a lower electrode region 26 reaching the buried layer 22 from the surface of the epitaxial layer 23. Since the isolation region 24 is formed by saturated diffusion, the surface concentration of the lower electrode region 26 is around 10 ¹⁸ atoms·cm ⁻² , which is sufficient to withstand use as a lower electrode of an MIS type capacitor.

Next, as shown in FIG.
By selectively implanting or diffusing boron B into the surface of the substrate, a base region 27 that will become the base of the NPN transistor is formed.

Next, as shown in FIG. 2D, an epitaxial layer 2 is formed.
The oxide film 28 on the surface of the third surface is selectively etched to expose a part of the surface of the lower electrode region 26, and a film thickness of several hundred to several thousand hundreds is etched over the entire surface of the epitaxial layer 23 using a technique such as atmospheric pressure CVD. Deposit a silicon nitride film (Si ₃ N ₄ ) with a thickness of 1.5 μm. Since a silicon nitride film exhibits a higher dielectric constant than a silicon oxide film, it is possible to form a large capacitance. Then, a well-known resist pattern is formed on the surface of the silicon nitride film, and a dielectric thin film 29 is formed to cover the surface of the exposed lower electrode region 26 using a technique such as dry etching.
form. After that, cover the dielectric thin film 29.
An oxide film 28 is deposited by CVD method.

Next, as shown in FIG. 2E, holes are opened in the oxide film 28 on the surface of the base region 27 and the surface of the island 25 of the NPN transistor, and phosphorus (P) is selectively diffused using the oxide film 28 as a mask to form an N ⁺ An emitter region 30 and a collector contact region 31 are formed.

Next, as shown in FIG. 2F, a resist pattern is formed on the oxide film 28 using a negative or hard type photoresist, the oxide film 28 on the dielectric thin film 29 is removed, and then wet or dry etching is performed. A contact hole for electrical connection is opened in a desired portion of the oxide film 28. And board 2
An aluminum layer is formed on the entire surface by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode 32 of a desired shape and an upper electrode 33 on the dielectric thin film 29.

According to the manufacturing method of the present application described above, since the lower electrode region 26 formed by the diffusion process of the isolation region 24 is used as the lower electrode forming the MIS type capacitor, the manufacturing process of the dielectric thin film 29 is performed by emitter diffusion. It can be installed before the process. Then, there is no need to perform heat treatment for forming the MIS type capacitor between the phosphorus P deposit for forming the emitter region 30 and the phosphorus (P) drive-in, and the phosphorus (P) is initially diffused by the deposit. The heat treatment (drive-in) process for controlling the h _FE (current amplification factor) of the NPN transistor can be performed immediately from this state. Therefore, the variation in h _FE of the NPN transistor is small, and due to the inclusion of MIS type capacitance,
h It can solve the difficulty of _FE control. Also,
Since the heat treatment conditions for the emitter region 30 can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

The present invention is not limited to the embodiment shown in FIG. 1, but can also be applied to semiconductor integrated circuits using upper and lower separation techniques. Furthermore, in the case where the upper and lower separation techniques are used, the upper diffusion layer 35 of the upper and lower separation regions 34 is not used for both the upper and lower regions as in the second embodiment shown in FIG.
It is also conceivable to form the lower electrode region 26 by using only the same. In this case, since the lower electrode region 26 does not reach the buried layer 22, electrical insulation from the substrate 21 can be achieved.

(G) Effects of the invention As explained above, according to the present invention, the MIS type capacitor is added as an optional device.
Since there is little variation in the h _FE of the NPN transistor, there is an advantage that it is possible to provide a method of manufacturing a semiconductor integrated circuit in which the h _FE of the NPN transistor can be extremely easily controlled. In addition, since the processing conditions for the emitter area 30 can be unified for models that incorporate MIS type capacity and models that do not, process management for each model can be simplified, and wafers of different models can be placed in the same diffusion furnace. Heat treatment also has the advantage of making it possible to produce a wide variety of products in small quantities. Further, according to the present application, since the lower electrode region 26 is formed using the diffusion process of the isolation region 24, the process can be simplified, and in the first embodiment, the buried layer 22 is used, so the lower electrode region 26 is formed. It also has the advantage that it can be electrically insulated from the substrate 21.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention, FIGS. 2A to 2F are cross-sectional views for explaining the manufacturing method of the present invention, and FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention. FIG. 4 is a sectional view for explaining a conventional example. 21 is the P-type semiconductor substrate, 26 is the lower electrode region of the MIS-type capacitor, 27 is the P-type base region of the NPN transistor, 29 is the dielectric thin film, 30 is the N ⁺ -type emitter region of the NPN transistor, and 33 is the MIS-type capacitor. This is the upper electrode.

Claims (1)

[Claims] 1. A step of forming a buried layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type; a step of forming an epitaxial layer of an opposite conductivity type on the substrate; By selectively diffusing conductive type impurities, isolation regions for forming multiple islands are formed, and
forming a lower electrode region by diffusing the impurity of one conductivity type also on the island surface where the MIS type capacitive element is to be formed; forming an exposed opening and forming a dielectric thin film of the MIS type capacitive element made of a silicon nitride film by CVD method so as to cover the opening; forming an emitter region on the surface of the base region of the bipolar transistor by selectively diffusing conductive type impurities; coating the entire surface with an electrode material and patterning it to cover the top of the dielectric thin film; A method of manufacturing a semiconductor integrated circuit, comprising the step of forming an upper electrode and an electrode in contact with each diffusion region.