JPH0583193B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a manufacturing method that facilitates _hFE control of an NPN transistor in a semiconductor integrated circuit incorporating an MIS type capacitive element.

(b) Conventional technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base and an emitter are double-diffused on the surface of a semiconductor layer that serves as a collector. Therefore, the base and emitter diffusion processes for manufacturing the NPN transistor are essential processes, as well as the high-concentration buried layer formation process and epitaxial layer growth process to reduce the collector series resistance, and the junction separation of each element. This is an essential process (basic process) for manufacturing bipolar ICs, along with the isolation region formation process for electrical connection and the electrode formation process for electrical connection.

On the other hand, due to circuit requirements, other elements, such as
There is a demand for incorporating PNP transistors, resistors, capacitors, Zener diodes, etc. on the same board. In this case, it goes without saying that it is preferable to utilize this process as much as possible in terms of process simplification. However, since the conditions for the base and emitter diffusion steps are set with the most important consideration given to the characteristics of the NPN transistor, it is often difficult to integrate the base and emitter diffusion steps using only the basic steps. Therefore, without aiming to form a basic NPN transistor,
A new process may be added for the purpose of incorporating other elements or improving the characteristics of other elements. For example, a P ⁺ diffusion process to form an anode region that controls the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process to form a resistance region with a different resistivity from the base region, and an implant resistor. forming process,
These include the nitride film formation process to form a nitride film capacitor that provides a larger capacitance than the MOS type, and the collector low resistance region formation process to further reduce the collector series resistance of NPN transistors, all of which are used for bipolar ICs. This is a process (optional process) in which it is decided whether or not to add it based on consideration of the process, purpose, and cost.

FIG. 3 shows an MIS type capacitor formed using the above optional process. In the figure, 1 is a P-type semiconductor substrate, 2 is an N-type epitaxial layer, and 3 is an N ⁺
4 is a P ⁺ type isolation region, 5 is an island,
6 is the N ⁺ type lower electrode region due to emitter diffusion;
7 is a silicon nitride film (Si ₃ N ₄ ) as a high dielectric constant insulator, 8 is an upper electrode made of aluminum material, 9 is an oxide film, and 10 is an electrode. Furthermore, as an MIS type capacitor using a nitride film, for example,
-Described in Publication No. 244056.

(c) Problems to be solved by the invention However, since conventional MIS type capacitors use the emitter region of the NPN transistor as the lower electrode, a nitride film is formed after depositing N-type impurities to form the emitter region. After that, drive-in of N-type impurities must be performed. Then, because the heat treatment at around 800℃ used for depositing the nitride film diffuses the emitter region, the NPN transistor's h _FE (current amplification factor) varies greatly, making it difficult to control.

In addition, it is necessary to change the heat treatment conditions for the emitter region depending on whether or not the optional process necessary for forming the nitride film is added, so process management is required for each model, which has the disadvantage that management cannot be standardized. Ta.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and includes a step of forming the lower electrode region 26 of the MIS type capacitor simultaneously with the step of forming the isolation region 24, and a step of forming the lower electrode region 26 on the surface of the lower electrode region 26. A process of patterning the oxide film 28 and partially exposing it, and selectively exposing the oxide film 28 using the pattern.
The method includes a step of introducing a type impurity, a step of forming a dielectric thin film 29 on the surface of the exposed lower electrode region 26, and a step of diffusing an emitter region 30 of the NPN transistor after forming the dielectric thin film 29. It is characterized by

(E) Effect According to the present invention, since the separation region 24 is used as the lower electrode of the MIS type capacitor, the nitride film can be deposited before the emitter diffusion step, and the NPN transistor after the emitter region 30 is formed can be deposited. h Heat treatment that causes _FE variation can be eliminated. Furthermore, since the P-type impurity is ion-implanted or deposited using the oxide film pattern for nitride film (Si ₃ N ₄ ) deposition, the resistance component of the lower electrode region 26 under the dielectric thin film 29 can be reduced.

(F) Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, the surface of a P-type silicon semiconductor substrate 21 is selectively doped with N-type impurities such as antimony (Sb) or arsenic (As) to form N ⁺
A mold embedding layer 22 is formed to a thickness of 5 to 50% over the entire surface of the substrate 21.
A 10 μm N-type epitaxial layer 23 is laminated.

Next, as shown in FIG. 1B, by selectively diffusing boron (B) from the surface of the substrate 21, ^P A separation region 24 is formed. The epitaxial layer 23 surrounded by the isolation region 24 becomes an island 25 for forming each circuit element. At the same time, boron (B) in the separation region 24 diffusion process
is also diffused into a region corresponding to the buried layer 22 on the surface of the island 25 to form a lower electrode region 26 reaching the buried layer 22 from the surface of the epitaxial layer 23. Since the isolation region 24 is formed by saturated diffusion and penetrates the epitaxial layer 23, the impurity concentration on its surface is approximately 10 ¹⁸ atoms·cm ⁻² . Further, the bottom of the lower electrode region 26 is formed so as to be entirely in contact with the buried layer 22, and the buried layer 22 covers the bottom of the lower electrode region 26.
is electrically insulated from the ground potential of the substrate 21. Therefore, since the MIS type capacitor is electrically independent, there are no restrictions on the circuit configuration.

Next, as shown in FIG.
By selectively ion-implanting or diffusing boron (B) into the surface of the substrate, a base region 27 that will become the base of the NPN transistor is formed. Thereafter, an oxide film 28 is formed on the surface of the epitaxial layer 23 by thermal oxidation or CVD, and an oxide film pattern having openings is formed on a part of the surface of the lower electrode region 26 using a positive or negative photoresist. Then, using this oxide film pattern, boron (B) ions are selectively implanted or deposited onto the surface of the lower electrode region 26. In this step, the impurity concentration of boron (B) on the surface of the lower electrode region 26 is increased to around 10 ²⁰ atoms·cm ⁻² . Therefore, the resistance component of the lower electrode region 26 can be reduced.

Next, as shown in FIG. 1D, an epitaxial layer 2 is formed.
3. A silicon nitride film (Si ₃ N ₄ ) with a thickness of several hundred to several thousand Å is deposited on the entire surface using a technique such as atmospheric pressure CVD, and the exposed lower electrode area is removed using a technique such as dry etching. Dielectric thin film 29 covering the surface of 26
form. Silicon nitride film (Si ₃ N ₄ ) has a higher dielectric constant than silicon oxide film (SiO ₂ ), so
It is possible to form a large capacity. After that, an oxide film 2 is formed by CVD to cover the dielectric thin film 29.
Deposit 8.

Next, as shown in FIG. 1E, holes are opened in the oxide film 28 on the surface of the base region 27 and the surface of the island 25 of the NPN transistor, and phosphorus (P) is selectively diffused using the oxide film 28 as a mask. ⁺ type emitter region 30 and collector contact region 31
form.

Next, as shown in FIG. 1F, a resist pattern of negative or positive photoresist is formed on the oxide film 28, the oxide film 28 on the dielectric thin film 29 is removed, and oxidized by wet or dry etching. A contact hole for electrical connection is opened in a desired portion of the film 28. Then, an aluminum layer is formed on the entire surface of the substrate 21 by a well-known vapor deposition or sputtering technique, and this aluminum layer is patterned again to form an electrode 32 of a desired shape and an upper electrode 33 on the dielectric thin film 29.

According to the manufacturing method of the present application described above, since the diffusion process of the isolation region 24 is used to form the lower electrode of the MIS type capacitor, the lower electrode of the MIS type capacitor can be formed without any additional process. The manufacturing process of the dielectric thin film 29 can be placed before the emitter diffusion process. Then, emitter area 3
There is no need to perform heat treatment for MIS type capacitance formation between the phosphorus (P) deposit for 0 formation and the phosphorus (P) drive-in, and the phosphorus (P) is initially diffused by the deposit. of NPN transistor immediately from
h Heat treatment (drive-in) process for _FE (current amplification factor) control can be performed. Therefore, the variation in h _FE of NPN transistors is small, and the difficulty in controlling h _FE caused by incorporating MIS type capacitors can be solved. Furthermore, since the heat treatment conditions for the emitter region 30 can be unified for models that incorporate MIS type capacitors and models that do not, process management for each model becomes extremely easy.

Furthermore, since the P-type impurity is introduced into the surface of the lower electrode region 26 immediately before the nitride film is deposited, the resistance component of the lower electrode can be reduced, and the voltage dependence, frequency dependence, and hysteresis characteristics of the MIS type capacitance can be reduced. Moreover, since the P-type impurity is introduced using the oxide film pattern for forming the dielectric thin film 29,
The process can be simplified.

The present invention is not limited to the embodiment shown in FIG. 1, but can also be applied to semiconductor integrated circuits using upper and lower separation techniques. Furthermore, in the case where the upper and lower separation techniques are used, the upper diffusion layer 35 of the upper and lower separation regions 34 is not used in both the upper and lower regions as in the second embodiment shown in FIG.
It is also conceivable to form the lower electrode region 26 by using only the same. In this case, since the lower electrode region 26 does not reach the buried layer 22, electrical insulation from the substrate 21 can be achieved.

(G) Effects of the invention As explained above, according to the present invention, the MIS type capacitor is added as an optional device.
Since there is little variation in h _FE of NPN transistors, there is an advantage that a method for manufacturing a semiconductor integrated circuit can be provided in which control of h _FE of NPN transistors is extremely easy. In addition, since the processing conditions for the emitter area 30 can be unified for models that incorporate MIS type capacity and models that do not, process management for each model can be simplified, and wafers of different models can be processed in the same diffusion furnace. It also has the advantage of being able to produce a wide variety of products in small quantities when heat treated.

Then, a lower electrode region 26 is placed immediately before the nitride film deposition.
Since P-type impurities are introduced to the surface, voltage dependence,
Since an MIS type capacitor with good characteristics and small hysteresis can be incorporated, and impurities are introduced using the oxide film pattern for forming the dielectric thin film 29, the process can be simplified.

[Brief explanation of drawings]

1A to 1F are sectional views for explaining the present invention, FIG. 2 is a sectional view for explaining a second embodiment of the invention, and FIG. 3 is for explaining a conventional example. FIG. 21 is the P-type semiconductor substrate, 26 is the lower electrode region of the MIS-type capacitor, 27 is the P-type base region of the NPN transistor, 29 is the dielectric thin film, 30 is the N ⁺ -type emitter region of the NPN transistor, and 33 is the MIS-type capacitor. This is the upper electrode.

Claims (1)

[Claims] 1. A step of forming a buried layer of an opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type; a step of forming an epitaxial layer of an opposite conductivity type on the substrate; forming a plurality of islands by forming isolation regions of one conductivity type from the layer surface, and forming a lower electrode region of an MIS type capacitor on the surface of one island by the step of forming the isolation regions; a step of opening a part of an insulating film covering the surface of the electrode region to expose the surface of the lower electrode region; using the opening of the insulating film to selectively coat the surface of the lower electrode region with one conductivity type; a step of ion-implanting impurities; depositing a silicon nitride film to cover the opening;
a step of forming a dielectric thin film of an MIS type capacitive element; a step of forming an emitter region of the vertical bipolar transistor by diffusing impurities of opposite conductivity type into the surface of the region that will become the base of the vertical bipolar transistor; A semiconductor integrated circuit comprising the steps of: coating the entire surface with an electrode material and patterning it to form an upper electrode covering the dielectric thin film and an electrode contacting each diffusion region. manufacturing method.