JPH061812B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit incorporating an MIS type capacitance element, which facilitates h _FE control of an NPN transistor.

(B) Conventional Technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base / emitter is double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are indispensable steps, and a high-concentration buried layer forming step for reducing collector series resistance, an epitaxial layer growing step, and junction separation for each element. This is a step (basic step) essential for manufacturing a bipolar IC along with the isolation region forming step, the electrode forming step for electrical connection, and the like.

On the other hand, there is a demand for incorporating other elements such as a PNP transistor, a resistor, a capacitor, and a Zener diode on the same substrate in view of circuit requirements. In this case, needless to say, it is preferable to divert the basic process as much as possible from the viewpoint of simplifying the process. However, in the base and emitter diffusion process, since various conditions are set with the characteristics of the NPN transistor as the most important factor, integration is often difficult only by the basic process. So, basic NP
A new process may be added for the purpose of incorporating another element or improving the characteristics of another element without forming the N-transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of the base region, and an implantation process. A low resistance forming step, a nitride film forming step for forming a nitride film capacitor that provides a larger capacity than that of a MOS type, a collector low resistance region forming step for further reducing the collector series resistance of an NPN transistor, and the like. This is a process (optional process) in which it is determined whether or not to add the bipolar IC by considering the use and purpose and cost of the bipolar IC.

FIG. 4 shows an example of a conventional MIS type capacitor formed by using the above optional process. In the figure, (1) is a P type substrate, (2) is an N type epitaxial layer, (3) is an N ⁺ type buried layer, (4) is a P ⁺ type isolation region, (5) is an island, (6) ) Is an N ⁺ type lower electrode region of MIS type capacitance due to emitter diffusion, (7)
Is a silicon nitride film (Si ₃ N ₄ ) as a dielectric thin film, (8) is an upper electrode, (9) is an oxide film, and (10) is an electrode. An MIS type capacitor using a nitride film is disclosed in, for example, Japanese Patent Laid-Open No. 60-2440
No. 56 publication.

(C) Problems to be Solved by the Invention However, since the conventional MIS-type capacitor uses the lower electrode region (6) by the emitter diffusion, the dielectric thin film (7) is formed after the emitter region of the NPN transistor is formed. The forming process must be arranged. Then, the heat treatment at about 800 ° C. of the CVD used for forming the nitride film diffuses the emitter region. Therefore, even if the drive-in step of the emitter region is arranged after the nitride film is formed, the h _FE of the NPN transistor varies. It had a big drawback that its control was difficult.

In addition, it is necessary to change the drive-in condition of the emitter region depending on whether or not an optional process for incorporating the MIS type capacitor is added, which requires a process control for each model and cannot be standardized.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the epitaxial layer is formed after removing the thick oxide film (27) used for forming the isolation region.
(24) A step of newly forming a thin oxide film (29) on the surface, and a step of ion-implanting boron (B) which penetrates the oxide film (29) and forms the base region (31) of the NPN transistor. ,
Prior to the diffusion of the emitter of the NPN transistor, the step of forming the dielectric thin film (32) of the MIS type capacitor, and then the NPN
It is characterized in that the emitter region (34) of the transistor is formed by diffusion.

(E) Function According to the present invention, since the nitride film is formed prior to the diffusion of the emitter, it is possible to eliminate the extra heat treatment from the deposit of the emitter region (34) to the drive-in.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (2
N ⁺ -type buried layer (22) formed by selectively doping the N-type impurity of antimony (Sb) or arsenic (As) or the like on the surface of 1), the substrate surrounding the buried layer (22) ( 21) Boron (B) on the surface
Is doped to form a lower diffusion layer (23) which is vertically separated. After that, a thickness of 5 is formed on the entire surface of the substrate (21) by a known vapor deposition method.
An N-type epitaxial layer (24) of 10 μm is laminated.

Next, as shown in FIG. 1B, boron (B) is selectively diffused from the surface of the epitaxial layer (23) to form the epitaxial layer (24).
A plurality of islands (25) are formed by separating the junctions. (26) is an upper diffusion layer that is separated into upper and lower parts, and (27) is an oxide film.

At the same time, by using the diffusion process of the upper diffusion layer 26, M
A lower electrode region (28) to be the lower electrode of the IS type capacitor is formed. According to the present embodiment, the steps can be shared, so that the steps can be simplified. Of course, the P ⁺ -type diffusion region may be used alone, or the anode forming process of the Zener diode may be used, and may be performed before or after the subsequent base diffusion process. Also,
Regardless of the diffusion depth of the lower electrode region (28), it is desirable that the impurity concentration is a high impurity concentration, for example, 10 ¹⁸ atoms · cm ⁻² or more in view of the hysteresis of the MIS type capacitance. Since the boron (B) drive-in in this step is performed for a long time in an oxidizing atmosphere, a thick oxide film (27) having a film thickness of 5000 to 8000Å is formed on the surface of the epitaxial layer (24).

Next, as shown in FIG. 1C, the thick oxide film (27) is removed by 10%.
Completely remove with an HF solution, etc.
4) Expose the surface. Then, thermal oxidation is performed again to form a new thin oxide film (29) having a film thickness of several hundred to 1000 Å on the surface of the epitaxial layer (24). Since the step formed during the deposition of boron (B) remains on the surface of the epitaxial layer (24), the step also appears on the surface of the thin oxide film (29). Therefore, the subsequent mask alignment can be performed.

Next, as shown in FIG. 1D, a positive or negative photoresist is spin-on coated, exposed, and developed on the oxide film (29) on the surface of the epitaxial layer (24) to develop a first resist pattern of a desired shape ( 30) is formed. After that, boron (B) is selectively ion-implanted through the oxide film (29) using the resist pattern (30) as a mask to form a base region (31) of the NPN transistor on the surface of the island (25). By implanting boron (B) into the surface of the lower electrode region (28) by using this step, the impurity concentration on the surface of the lower electrode region (28) can be improved. Also, a thin oxide film (2
Since the heat treatment can be performed in a non-oxidizing atmosphere by leaving 9), crystal defects do not occur on the surface of the epitaxial layer (24).

Next, as shown in FIG. 1E, the oxide film (29) on the surface of the epitaxial layer (24) is selectively removed by etching to remove the lower electrode region.
(28) Part of the surface is exposed, and a silicon nitride film (Si ₃ N ₄ ) having a film thickness of several hundred to several thousand hundred Å is deposited on the entire surface of the epitaxial layer (24) by using a technique such as atmospheric pressure CVD. . Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, it is possible to form a large capacity. Then, a known resist pattern is formed on the surface of the silicon nitride film, and the exposed lower electrode region (28) is formed by using a technique such as dry etching.
A dielectric thin film (32) covering the surface of the is formed.

Next, as shown in FIG. 1F, an oxide film (33) having a film thickness of several thousand Å is formed on the entire surface by CVD so as to cover the dielectric thin film (32).
A heat treatment (baking) for firing the oxide film (33) is performed. By the way, diffusion (drive-in) of the base area (31)
May be performed at the stage of FIG. 1D, but since the base region (31) is covered with a thin oxide film (29) during the process, it should be performed in common with the heat treatment of this step after ion implantation. Is also possible.

Next, as shown in FIG. 1G, the oxide film (33) on the surface of the base region (31) and the surface of the island (25) of the NPN transistor this time.
Is opened, and phosphorus (P) is deposited by using this oxide film (33) as a mask to form an N ⁺ type emitter region (34) and a collector contact region (35). Thereafter, the emitter region 36 is diffused (drive-in) to a desired depth by applying a heat treatment in an oxidizing or non-oxidizing atmosphere. Incidentally, when phosphorus (P) is deposited on the surface of the nitride film (Si ₃ N ₄ ), both react with each other to form glass, so that the dielectric thin film (32) is reduced by protecting it with a CVD oxide film (33). Prevent.

Next, as shown in FIG. 1H, a resist pattern made of a negative or positive type photoresist is formed on the oxide film (33),
Dielectric thin film by wet or dry etching (32)
The upper oxide film (33) is removed, and a contact hole for electrical connection is opened in a desired portion of the oxide film (33). Then, an aluminum layer is formed on the entire surface of the substrate (21) by a known vapor deposition or sputtering technique, and the aluminum layer is patterned again to form an electrode (36) having a desired shape and an upper electrode (37) on the dielectric thin film (32). ) Is formed.

According to the manufacturing method of the present application described above, the dielectric thin film (3
2) is formed, phosphorus (P) for forming the emitter region (34) is formed.
There is no need to place a heat treatment for incorporating an optional device between the deposit and the drive-in of phosphorus (P).
Therefore, there is little variation in the emitter region (34), so the NPN
The variation in h _FE of the transistor can be significantly suppressed and the control thereof can be facilitated. Further, since the heat treatment conditions for the emitter region (34) can be unified regardless of whether or not the optional device is incorporated, the process control for each model becomes extremely easy.

Further, according to the present invention, since the thick oxide film (27) generated at the time of forming the isolation region is removed and the thin oxide film (29) is attached again, ion implantation is performed by penetrating the thin oxide film (29). It can be performed. Therefore, it is not necessary to use an expensive device such as an RIE device for etching the thick oxide film (27) with high precision, and it is possible to prevent crystal defects on the surface of the epitaxial layer (24).

Further, since the surface of the base region (31) is covered with the thin oxide film (29), the drive-in of the base region (31) can be postponed, and by doing so, the CVD oxide film (3
It can be shared with baking in 3). Further CV
The impurity concentration of the base region (31) due to the D oxide film (33) is set to 20.
By setting a relatively low value of 0 to 400Ω / □, h _FE
Can be further suppressed.

By the way, the lower electrode region (28) of the MIS type capacitor of the present application takes various embodiments. FIG. 2 shows a second embodiment of the present application, which is an example applied to an IC of a normal separation type rather than upper and lower separation. As is clear from the figure, the lower electrode region (28) of the MIS type capacitor is formed at the same time as the formation of the isolation region (40), and the entire bottom surface of the lower electrode region (28) is made to collide with the buried layer (22). Has a structure in which the lower electrode of the MIS type capacitor is separated from the ground potential of the substrate (21). Further, FIG. 3 shows the third of the present application.
The present invention will be described with reference to FIG. 4 and an example applied to an IC having an N ⁺ type collector low resistance region (41) for the purpose of reducing V _CE (sat) of the NPN transistor. As is clear from the figure, the lower electrode region (28) of the MIS type capacitor may be formed at the same time when the collector low resistance region (41) is formed, and then the process of FIG. 1C may be performed.

(G) Effect of the Invention As described above, according to the present invention, there is an advantage that a method for manufacturing a semiconductor integrated circuit can be provided which can eliminate the difficulty of h _FE control of an NPN transistor by incorporating a MIS type capacitor. In addition, since the heat treatment conditions for the emitter region (34) can be unified, the process control for each model can be simplified, and there is an advantage that it is possible to heat treat different types of wafers at the same time and to produce multiple models in small quantities. Have.

And according to the present invention, a thin oxide film (29) which is newly formed
Since proceed step by utilizing also has the advantage that makes it easier to control the more h _FE by suppressing the depletion of the ease of manufacture and the base region (31) surface.

[Brief description of drawings]

1A to 1H are sectional views for explaining the present invention,
2 and 3 are sectional views for explaining the second and third embodiments of the present invention, and FIG. 4 is a sectional view for explaining the conventional example. (21) is a P-type substrate, (28) is a lower electrode region of the MIS-type capacitor, (29) is a thin oxide film, (31) is a base region of the NPN transistor, (32) is a dielectric thin film of the MIS-type capacitor,
(34) is an emitter region of the NPN transistor.

Claims (1)

[Claims] 1. A step of forming a buried layer of opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of opposite conductivity type on the substrate, and a separation for separating the epitaxial layer. Forming the lower electrode region of the MIS-type capacitor at the same time as forming the region or at the same time as forming the collector low resistance region of the vertical bipolar transistor; removing the thick oxide film formed on the surface of the epitaxial layer; Exposing the surface of the epitaxial layer and forming a relatively thin oxide film on the surface of the epitaxial layer again; forming a base region of the vertical bipolar transistor by ion-implanting impurities of one conductivity type through the thin oxide film. Step, forming an opening in the thin oxide film to expose a part of the surface of the lower electrode region, and covering the opening. Forming a dielectric thin film of the MIS type capacitor made of a silicon nitride film by a CVD method; forming an emitter region of the bipolar transistor by selectively diffusing an impurity of opposite conductivity type on the surface of the base region; A process for producing a semiconductor integrated circuit, comprising: a step of coating an electrode material and patterning the electrode material to form an upper electrode that covers the dielectric thin film and an electrode that contacts each diffusion region. Method.