JPH0831600B2 - Method for manufacturing MIS type semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a MIS type semiconductor device, and more particularly to a contact hole for a source / drain region and an electrode formed in this contact hole. Regarding the improvement of the structure of.

(Prior Art) In semiconductor integrated circuits, especially in MOS type integrated circuits, miniaturization and high integration of elements are aimed at, 1 micron or 1 micron.
MOS transistors with sub-micron effective channel lengths of sub-micron are used. The miniaturization of such elements has hitherto mainly depended on the reduction in size due to the progress of lithography technology. However, when the effective channel length of a MOS transistor reaches the level of 1 micron or submicron, high integration and high speed of the device can be achieved by simply reducing the dimensions of the gate electrode, wiring, impurity diffusion region, contact hole, etc. It is not possible to cope with the change. For example, there is a need for a self-aligned contact technique for forming contact holes between a metal wiring and impurity diffusion regions such as source and drain regions in a self-aligned manner with a gate electrode and an impurity diffusion region, respectively. By forming the impurity diffusion region and the contact hole for the metal wiring in a self-aligned manner with respect to the gate electrode and the impurity diffusion region, for example, the distance of the diffusion wiring in the source and drain regions is reduced and added to the transistor. The series resistance value decreases. Furthermore, since the distance between the gate and drain regions and the overlap margin of the field insulating film and the contact region can be reduced, the area of the element region, especially the diffusion region is reduced, and the electrostatic capacitance parasitic on the element is reduced. descend. Therefore, the operation speed of the device is improved by forming the contact hole in a self-aligned manner.

Next, the conventional method of forming contact holes in a self-aligned manner
A method of manufacturing the MIS type semiconductor device will be briefly described with reference to the drawings. FIG. 3 shows a MIS type semiconductor device, especially N
FIG. 6 is a cross-sectional view showing each step when manufacturing a channel MOS transistor. First, as shown in FIG. 3 (a), p
An element isolation insulating film 72 is formed on a silicon substrate 71 of a mold to provide an element region 73, a gate oxide film 74 is formed on the substrate surface of the element region 73, and then a polycrystalline silicon layer 75 is deposited and formed. The gate electrode 76 and the polycrystalline silicon wiring 77 are formed by using the photolithography technique. Further, phosphorus ions are implanted on the entire surface to form n-type low concentration diffusion layers 78 and 79. Next, as shown in FIG. 3 (b), a silicon oxide film 80 is deposited and formed on the entire surface by the CVD method and annealed. Next, as shown in FIG. 3 (c), the silicon oxide film 80 is removed by a film thickness to obtain a gate electrode.
The silicon oxide film 80 is left only on the side walls of the 76 and the polycrystalline silicon wiring 77. Then, using the gate electrode 76 and the silicon oxide film 80 as a mask, arsenic ions are implanted to form n-type high-concentration diffusion layers (n ⁺ ) 81 and 82. Next, FIG. 3 (d)
As shown in FIG. 3, a silicon oxide film 83 is deposited and formed on the entire surface by plasma CVD, and then a desired portion is covered with a resist 84. Next, as shown in FIG. 3E, the plasma CVD silicon oxide film 83 is etched with a predetermined etching solution using the resist 84 as a mask. Here, the plasma CVD silicon oxide film 83 is not heat-treated and has a weak composition. Since the etching rate of the silicon oxide film 83 in the flat portion is set to about 1/5 to 1/20 of the step portion of the gate electrode side wall, the silicon oxide film 83 of the step portion of the gate electrode side wall is removed,
Contact holes 85 and 86 are formed to reach the surfaces of the high-concentration diffusion layers 81 and 82, respectively. Next, after forming a contact hole (not shown) communicating with the gate electrode 76 on the field, a wiring metal material film such as aluminum is deposited on the entire surface, and this is patterned to form a wiring shown in FIG. ), A source wiring 87, a drain wiring 88, etc. are formed.

Conventionally, the contact holes 85 and 86 for the diffusion layers 81 and 82 are formed in a self-aligned manner in the vicinity of the gate electrode 76 by such a method. By forming the contact hole by such a method, the operating characteristics of the element (in this case, an N-channel MOS transistor) are improved as described above.

However, according to such a method, after the silicon oxide film 83 is formed by plasma CVD, the high temperature gettering step which is performed when manufacturing a normal MIS type semiconductor device cannot be performed. The reason is that when the high temperature gettering step is performed, the composition of the plasma CVD silicon oxide film 83 which is formed in a weak composition state in advance is improved and becomes stronger. The contact hole cannot be formed in the area. Further, in the subsequent process, aluminum is embedded in the opened contact hole to form a wiring, and if a high temperature gettering process is performed after forming this wiring, the wiring will be melted. Therefore, the gettering cannot be performed by the conventional method, and there is a problem in that the threshold voltage of the MIS transistor becomes abnormal due to the influence of the mobile ions existing in the plasma CVD silicon oxide film 83. Moreover, in the MIS transistor manufactured by the above method, stability against hot carrier stress during operation is poor, and for example, when the power supply voltage is 6 V, it takes about 100 hours for the drain current to drop to 10% of the initial value. It is short and extremely unreliable.

(Problems to be Solved by the Invention) As described above, in the related art, the gettering step cannot be performed in order to perform the step of forming the contact hole in a self-aligning manner, and thus the reliability of the semiconductor device manufactured by the method cannot be improved. There is a problem of becoming low.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a MIS that can manufacture a highly reliable semiconductor device in which wiring is not melted even when a gettering process is performed. It is to provide a method of manufacturing a semiconductor device.

[Structure of the Invention] (Means for Solving Problems) In the method of manufacturing an MIS type semiconductor device according to the present invention, an element isolation region is formed on the surface of a first conductivity type silicon semiconductor substrate to isolate it from other regions. And forming a gate electrode on the surface of the substrate in the element region via a gate insulating film in the element region, and matching the gate electrode with impurities of the second conductivity type to form the element. A third step of selectively introducing into the region to form a pair of relatively low-concentration second conductivity type first diffusion regions; and a wall made of a first insulating film so as to cover the side wall of the gate electrode. A step of forming a body,
After depositing the second insulating film on the entire surface, only the second insulating film in the vicinity of the stepped portion of the wall body is selectively removed to allow the second insulating film to reach the surface of the first diffusion region. A step of forming a pair of openings in a self-aligned manner, a step of filling each of the pair of openings with a silicon layer containing an impurity of the second conductivity type by an epitaxial growth method, and a step of heating each silicon layer By introducing impurities of two conductivity types, the impurity concentration is different so that the side in contact with the surface of each of the first diffusion regions has a low concentration and the surface side of the silicon layer has a high concentration.
A silicon layer having a layered structure is formed, and a second conductivity type impurity is diffused from each of the silicon layers to each of the first diffusion regions to form a second layer having a relatively high concentration on the surface of each of the first diffusion regions.
Forming second diffusion regions of conductivity type, and
And a step of gettering the movable ions contained in the insulating film.

(Operation) According to the present invention, the inside of the opening that communicates with the surface of the low-concentration diffusion region is filled with an epitaxial silicon layer containing a low-concentration impurity, and then, when the high-temperature gettering step is performed, In this way, a high concentration of impurities is introduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the element structure of an N-channel MOS transistor manufactured by the method for manufacturing a MIS type semiconductor device of the present invention. FIG. 1 (a) is a sectional view and FIG. 1 (b) is a pattern plane. It is a figure.

In FIG. 1, 11 is a p-type silicon substrate. A field insulating film 12 made of a silicon oxide film is embedded in the surface of the silicon substrate 11, and the field insulating film 12 separates the element region 13. A gate electrode 16 having a two-layer structure of a gate insulating film 14 and a polycrystalline silicon film 15 is formed on the substrate in the element region 13. The gate insulating film 14 is formed on the field insulating film 12.
Insulating film 14 and polycrystalline silicon film formed in the same process as
A polycrystalline silicon wiring layer 17 having a two-layer structure of 15 is formed. An insulating film 18 is formed on each of the gate electrode 16 and the wiring layer 17. Walls 19 and 20 made of a silicon insulating film are formed on the side wall of the gate electrode 16 and the side wall of the wiring layer 17, respectively.

In the element region 13, a pair of n-type low-concentration diffusion regions 21 and 22 are formed so as to be in contact with the channel region located under the gate electrode 16 on the substrate. Further, n-type high concentration diffusion regions 23 and 24 are formed on the surfaces of the low concentration diffusion regions 21 and 22. The low concentration diffusion region 21 and the high concentration diffusion region 23, and the low concentration diffusion region 22 and the high concentration diffusion region 24 are used as the source and drain regions of the MOS transistor.

A silicon insulating film 25 is deposited and formed on the field insulating film 12 and the gate electrode 16, and the silicon insulating film 25 has contact holes 26 and 27 communicating with the surfaces of the diffusion regions 23 and 24, respectively. A wall 19 made of a silicon insulating film provided on the side wall of the gate electrode 16
Is self-aligned with respect to. Then, inside the pair of contact holes 26 and 27, single crystal silicon layers 28 and 29 formed by an epitaxial growth method are buried, and the respective single crystal silicon layers 28 and 29 substantially contact holes 26 and 27. It has grown to the extent that it is completely filled, and the surface is flattened. Then, on the side of each of the single crystal silicon layers 28 and 29 that contacts the surface of the diffusion regions 23 and 24, the n-type impurity has a relatively low concentration, for example,
Low concentration region 30 diffused to about 10 ¹⁸ / cm ³ to 10 ¹⁹ / cm ³
The surface side of the diffusion regions 28 and 29 is a high concentration region 31 in which n-type impurities are diffused at a relatively high concentration, for example, about 10 ²⁰ / cm ³ . Further, the single crystal silicon layers 28 and 29 are
Wirings 32 and 33 made of an alloy film of aluminum and silicon are formed so as to be in contact with the respective surfaces. The wirings 32 and 33 are used as the source and drain wirings of the MOS transistor.

Although only shown in FIG. 1B, the contact hole 34 communicating with the surface of the polycrystalline silicon film 15 forming the gate electrode 16 is opened on the field insulating film. In this contact hole 34 also, a wiring 35 made of an alloy film of aluminum and silicon is formed. This wiring 35 is used as the gate wiring of the MOS transistor.

In the MOS transistor having such a structure, the single crystal silicon layer is formed on the surfaces of the pair of n-type diffusion regions 23 and 24 for the source and drain through the pair of contact holes 26 and 27, respectively.
28 and 29 are connected. This single crystal silicon layer 28, 29
Unlike a wiring material such as aluminum, does not dissolve even after a process involving high temperature heat treatment such as a gettering process. Therefore, in the MOS transistor having such a configuration, the gettering step can be performed during the manufacturing process. As a result, contained in the silicon insulating film 25,
It is possible to remove mobile ions that cause deterioration of device characteristics as described above.

Next, the method of the embodiment of the present invention will be described in the order of steps with reference to the sectional view of FIG.

First, for example, a p-type silicon semiconductor substrate 41 having a specific resistance of 10 to 20 Ωcm is prepared, and a field insulating film 42 for element isolation having a thickness of 0.6 μm is embedded on the surface of the substrate to form an element region 43 separately. Next, a thermal oxidation process is performed to form a 300 Å thick gate insulating film 44 on the substrate surface in the element region 43. Subsequently, for the purpose of controlling the threshold voltage of the manufactured MOS transistor, boron ions (B) are accelerated at a voltage of 70 KeV and a dose of 3.0.
Ions are implanted in the vicinity of the channel region formation planned portion of the element region 43 under the condition of × 10 ¹² / cm ² . Continuously, ρ is 200Ω on the entire surface
A polycrystalline silicon layer 45 having a thickness of 4,000 and a thickness of 4000 Å is deposited and formed. Further, the surface of the polycrystalline silicon layer 45 is oxidized in an oxygen atmosphere at a temperature of 950 ° C. to form a silicon oxide film 46, and then a silicon nitride film 47 having a thickness of 150 Å is formed on the entire surface by a low pressure CVD method. Further subsequently, the substrate is treated in a hydrogen combustion atmosphere at 950 ° C. for 60 minutes to form a silicon oxide film 48 containing nitrogen on the surface of the silicon nitride film 47, and a silicon oxide film 46 on the polycrystalline silicon layer 45. , Silicon nitride film 4
7. A composite film 49 consisting of the silicon oxide film 48 is formed {FIG. 2 (a)}.

Next, the above composite film 4 is formed by a well-known lithography technique.
9. The polycrystalline silicon layer 45 and the gate insulating film 44 are patterned to form a gate electrode 50 having a double structure of the gate insulating film 44 and the polycrystalline silicon layer 45 on the element region 43 on the field insulating film 42. Is a gate insulating film 44 and a polycrystalline silicon layer
Polycrystalline silicon wirings 51 each having a double structure of 45 are formed. At this time, the composite film 49 patterned in the same shape as the gate electrode 50 and the wiring 51 is left. Then, using the gate electrode 50 as a mask, phosphorus (P) is applied to the substrate surface of the element region 43 at 60 KeV, 1 × 10 ¹³ / cm 2.
Ion-implanted at a concentration of ² , and similarly arsenic (As) 40K
Ion implantation is performed at a concentration of eV and 1 × 10 ¹⁴ / cm ² {Fig. 2 (b)}.

Next, the substrate is oxidized in an oxygen atmosphere at 950 ° C. to activate the ions implanted in the above step to form the low-concentration diffusion layers 52 and 53, and at the same time, to make the surface 200 Å thick.
After forming a silicon oxide film (not shown) to a certain extent,
A silicon oxide film 54 is formed on the entire surface of the substrate by the low pressure CVD method {FIG. 2 (c)}.

Then, after annealing the silicon oxide film 54 at 900 ° C. for 10 minutes, the silicon oxide film 54 is etched by anisotropic dry etching. By this etching process, the walls 54 and 55 made of the silicon oxide film 54 are left only on the side wall of the gate electrode 50 and the side wall of the wiring 51 {second
Figure (d)}. After this, if necessary, an impurity step of diffusing arsenic or phosphorus at a high concentration in the diffusion wiring formation planned region may be performed.

Next, a silicon oxide film 56 having a thickness of about 7,000 Å is deposited and formed on the entire surface of the substrate by plasma CVD {FIG. 2 (e)}.

Further, after applying a photoresist to the plasma silicon oxide film 56 to a uniform thickness, the photoresist is applied to the gate electrode 50 by a photolithography method.
Then, a photoresist mask 57 is formed by turning in such a shape that the exposed portion is exposed. Next, using this mask 57, the entire surface of the substrate is etched with an etching solution composed of a mixed solution of NH ₄ F and HF or a diluted HF solution for about 1 minute.
Since the etching rate of the plasma silicon oxide film 56 in the portion deposited on the step portion of the gate electrode 50 is 5 to 20 times faster than that on the flat portion, it is deposited on the step portion. Partial plasma silicon oxide film
Only 56 is removed by this etching treatment, and a pair of narrow groove-shaped contact holes 58 and 59 communicating with the surfaces of the low-concentration diffusion layers 52 and 53, respectively, are provided on the side wall of the gate electrode 50 in advance. Are self-aligned with respect to. Since the etching plate of the silicon oxide film forming the wall body 54 provided on the side wall of the gate electrode 50 is much slower than the plasma silicon oxide film 56, the wall body 54 is removed by the above etching process. There is no fear of being killed. Further, since the step portion of the plasma silicon oxide film 56 on the wiring 51 is covered with the photoresist mask 57, it is not etched away either (FIG. 2 (f)). In this step, instead of the plasma silicon oxide film 56, it is also possible to use a silicon oxide film formed by sputtering, which has an etching rate higher in the step portion than in the flat portion.

Next, after removing the photoresist mask 57, HCl is added to SiH ₂ Cl ₂ using H ₂ as a carrier gas to perform epitaxial growth, and the pair of contact holes 58 and
Single crystal silicon layers 60, 61 are grown in 59. The growth temperature at this time is 900 ° C., PH ₃ is used as a doping gas, and the concentration of doped impurities is 10 ¹⁷ to 10 ¹⁹ / cm ³ (FIG. 2 (g)).

After that, in order to getter the movable ions in the plasma silicon oxide film 56, and to increase the impurity concentration on the surfaces of the single crystal silicon layers 60 and 61 embedded in the contact holes 58 and 59, in a later step. In order to improve the ohmic contact between the formed aluminum and wiring made of an alloy film of silicon, the entire surface of the substrate is exposed to an atmosphere of POcl ₃ at 900 ° C. for 30 minutes. As a result, a phosphorus glass layer (not shown) containing a high concentration of phosphorus is formed on the surface of the plasma silicon oxide film 56, and at the same time, a single crystal silicon layer is formed.
A high-concentration region 62 in which phosphorus is doped to about 10 ²⁰ / cm ³ is formed on the surface sides of 60 and 61, respectively, and the side of the single-crystal silicon layers 60 and 61 that contacts the surface of the diffusion layers 52 and 53. A low-concentration region 63 in which phosphorus is doped to about 10 ¹⁸ / cm ³ is formed in each of the regions. At the same time, the low concentration diffusion layer 52
Impurities contained in the single crystal silicon layers 60 and 61 are diffused on the surfaces of and 53 to form high-concentration diffusion layers 64 and 65. As a result, the source and drain regions have LDD (Lig
htly Doped Drain) structure. After that, an alloy film made of aluminum and silicon is deposited on the entire surface to a thickness of about 8000Å, and then patterning is performed using photolithography technology to form the source wiring 66, the drain wiring 67, etc. 2 (h)}.

According to such a manufacturing method, the gettering step can be carried out even after the contact hole is filled with the conductive material (single crystal silicon layer containing impurities), whereby the movable ions in the plasma silicon oxide film can be carried out. Can be gettered. As a result, in the MOS transistor manufactured by this manufacturing method, it is possible to solve all the problems of stability against the abnormal threshold voltage and the hot carrier stress at the time of operation, which have been conventionally problems.
The reliability is greatly improved.

Further, in combination with a self-aligning contact hole opening technique, the parasitic resistance and the parasitic capacitance of the semiconductor device can be significantly reduced, whereby high integration and high speed of the device can be realized. It is possible.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above-described embodiment, the case where the MIS type semiconductor device is an N-channel MOS transistor has been described, but it goes without saying that this can also be implemented for a P-channel MOS transistor. That is, in this case, the substrate is an n-type or an n-well region provided in a p-type substrate is used, and a gate electrode is formed on the surface of the n-type substrate or the n-well region, and then the gate is formed. By implanting B (boron) or BF ions using the electrode as a mask
Form a pair of diffusion regions of p ^- type. After forming the diffusion region, a pair of contact holes are opened in the same manner as in the above-described embodiment, and then H ₂ is used as a carrier gas for SiH ₂ cl ₂ and Hcl.
A silicon layer is epitaxially grown in the contact hole while adding B ₂ H ₆ gas to the mixed gas. As a result, the epitaxially grown silicon layer is doped with boron. However, in this case, after epitaxially growing the silicon layer, deposit a CVD film on the entire surface at about 3000 Å and perform a gettering process for 60 minutes in the atmosphere of POcl ₃ at 900 ° C. A step of removing and a step of ion-implanting boron into the epitaxially grown silicon layer to obtain a high concentration p ⁺ type are required.

Further, when the present invention is applied to a complementary semiconductor device forming both N-channel and P-channel MOS transistors, it is difficult to simultaneously grow a silicon epitaxial layer doped with impurities having different conductivity types in a contact hole. . However, in such a case, it can be realized by growing the silicon epitaxial layer without doping the impurities and then sequentially doping the necessary conductivity type impurities by changing the mask. At this time, the surface side of the silicon epitaxial layer was heavily doped with impurities (10 ²⁰ / cm ³ ) and the side in contact with the diffusion region had a low concentration (10 ²⁰ / cm ³ ).
Doping impurities to ¹⁸ / cm ³ to 10 ¹⁹ / cm ³ ) is important for integrating various MIS semiconductor positions having different depths and sizes of contact holes.

Further, in the above embodiment, the LDD structure is formed by forming the low-concentration diffusion region in advance and simultaneously forming the high-concentration diffusion region on the surface of the low-concentration diffusion region in the subsequent gettering step. However, in the MIS type semiconductor device, the diffusion region is used not only as the source and drain regions of the transistor but also as the diffusion wiring. In this case, it is preferable that the diffusion wiring have a resistance as low as possible. For example, the sheet resistance of a low concentration diffusion layer of about 2 × 10 ¹⁸ / cm ³ (depth is about 0.2 μm) is about 1 KΩ / □,
On the other hand, the sheet resistance of the high concentration diffusion layer of about 2 × 10 ²⁰ / cm ³ is about 50Ω / □. However, such a high concentration diffusion layer cannot be formed by the method of the above-mentioned embodiment, but can be easily formed by another method. That is, after forming the low-concentration diffusion region in the step of FIG. 2 (f), a step of implanting high-concentration ions such as arsenic and phosphorus through the contact hole is added to form the low-concentration diffusion region. A high-concentration diffusion region can be formed on the surface.

[Effects of the Invention] As described above, according to the present invention, the wiring is not melted even when the gettering step is performed, and a highly reliable semiconductor device can be manufactured. A method can be provided.

[Brief description of drawings]

FIG. 1 shows a structure of a semiconductor device manufactured by a method for manufacturing a MIS type semiconductor device according to the present invention. FIG. 1 (a) is a sectional view, FIG. 1 (b) is a pattern plan view, and FIG. FIG. 3 is a cross-sectional view sequentially showing the steps according to one embodiment of the method of manufacturing the MIS type semiconductor device of the present invention, and FIG. 3 is a cross-sectional view for explaining the conventional manufacturing method. 11,41 …… P-type silicon substrate, 12,42 …… Field insulating film, 13,43 …… Element region, 14,44 …… Gate insulating film, 1
5,45 …… Polycrystalline silicon layer, 16,50 …… Gate electrode, 17,
51 …… Polycrystalline silicon wiring, 19,20,54,55 …… Wall, 21,
22,52,53 …… Low-concentration diffusion region, 23,24,64,65 …… High-concentration diffusion region, 25,56 …… Plasma silicon oxide film, 26,2
7,58,59 …… Contact hole, 28.29,60,61 …… Single crystal silicon layer, 30,63 …… Low concentration region, 31,62 …… High concentration region, 32,66 …… Source wiring, 33, 67 …… Drain wiring.

Claims (2)

[Claims] 1. A step of forming an element isolation region on a surface of a first conductivity type silicon semiconductor substrate to form an element region isolated from other regions, and gate insulation on the surface of the substrate in the element region. A step of forming a gate electrode through a film, and a second conductivity type first impurity having a relatively low concentration by selectively introducing a second conductivity type impurity into the element region in alignment with the gate electrode. A third step of forming a diffusion region, a step of forming a wall body made of a first insulating film so as to cover a side wall of the gate electrode, and a step of depositing a second insulating film on the entire surface, and then the wall body Selectively removing only the second insulating film in the vicinity of the stepped portion of the second insulating film to form a pair of openings communicating with the surface of the first diffusion region in the second insulating film in a self-aligned manner, and epitaxial growth Second pair of openings by the method
A second conductivity type impurity is introduced into each of the silicon layers by a step of burying with a silicon layer containing conductivity type impurities and a heat step, and the side in contact with the surface of each of the first diffusion regions has a low concentration of silicon. A silicon layer having a two-layer structure having different impurity concentrations such that the surface side of the layer has a high concentration is formed, and a second conductivity type impurity is diffused from each of the silicon layers to each of the first diffusion regions. Forming a second diffusion region of a second conductivity type of relatively high concentration on the surface of the first diffusion region, and gettering the movable ions contained in the second insulating film. Method for manufacturing MIS type semiconductor device. 2. When manufacturing an N-channel or P-channel MIS type semiconductor device in each of the element regions, the step of filling each of the pair of openings with a silicon layer by an epitaxial growth method is performed in a state where no impurities are contained. The method for manufacturing an MIS type semiconductor device according to claim 1, wherein the conductive type impurities are sequentially introduced after changing the mask.