JPH0612617B2 - Pseudo static RAM - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory), for example, a dynamic RAM of a system that precharges by short-circuiting a pair of complementary data lines. It is related to the technology that is effectively used.

[Background technology]

Prior to the present invention, the inventors of the present application have proposed a pseudo-static RAM in which a change in an address signal is detected and various timing signals necessary for the operation of an internal circuit are formed (Japanese Patent Application No. 57-164831). ). That is, a dynamic memory cell composed of a capacitor for storing information in the form of an electric charge and an address selecting MOSFET is used, and its peripheral circuit is composed of a CMOS (complementary MOS) static type circuit, and the address signal By detecting a change and obtaining a necessary timing signal, it can be handled from the outside in the same manner as a static RAM. When the dynamic memory array is used in this way, the dynamic circuit portion such as the memory array is not precharged when the power is turned on. Therefore, each dynamic circuit is temporarily operated before writing or reading. It is necessary to provide a dummy cycle of the cycle.

Therefore, the inventor of the present application has considered a dynamic RAM that does not require the dummy cycle.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM capable of performing a write or read operation immediately after power is turned on.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a power-on is detected to generate a one-shot pulse, and the pulse signal causes a sense amplifier having a CMOS latch circuit configuration between complementary data lines in a memory array composed of dynamic memory cells to operate to operate the complementary data lines. By setting one to the power supply voltage level and the other to the ground potential of the circuit, the precharge circuit between the complementary data lines is subsequently operated to short-circuit the complementary data lines, and thereby the level of the power supply voltage is reduced to 1/2. It is designed to be charged.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a dynamic RAM according to the present invention.

Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a well-known semiconductor integrated circuit manufacturing technique, though not particularly limited thereto.
Terminals Din, Dout, A0-A17, ▲ ▼, ▲
▼, ▲ ▼ and Vcc, Vss are external terminals, and power is supplied to the terminals Vcc, Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array, and well-known 1MOS type memory cells each composed of a storage capacitor and an address selection MOSFET are arranged in a matrix as described later. In this embodiment, the memory cell is arranged in a two-intersection method in which the input / output node is coupled to either one of the pair of complementary data lines D, which are arranged in parallel. In this embodiment, since the levels of these complementary data lines immediately after the power is turned on are defined, each complementary data line has a MOSF as described later.
ET is provided.

The data line precharge circuit is shown by the circuit symbol PC. In the precharge operation of the memory array of this embodiment, the complementary data lines D and D are set to about Vcc by simply short-circuiting a pair of complementary data lines (the same applies to common complementary data lines described later) with MOSFETs as will be described later. It is intended to be an intermediate level of / 2. This allows
Compared to the one that charges up from 0 volt to Vcc level, the level change amount is small and the precharge MOS
Even if the gate voltage of the FET is a normal logic level (Vcc), the FET can be turned on in a sufficiently non-saturated state, so that the precharge operation can be performed at high speed and with low power consumption. As described above, since the precharge level is set to the intermediate level of about Vcc / 2, even when the memory cell is read, the switch MO of the memory cell is changed.
Even if a normal logic level (Vcc) is used as the gate voltage (word line selection voltage) of the SFET, the SFET can be turned on in a sufficiently non-saturated state. Therefore, the entire charge of the information storage capacitor can be read without using the bootstrap voltage. Is possible. Further, as the read reference voltage, by utilizing the precharge level of one data line in which the memory cell is not selected, the dummy cell forming the read reference voltage becomes unnecessary.

A circuit symbol SA is a sense amplifier, which is not particularly limited, but includes a pair of power switch MOSFETs composed of a P-channel MOSFET and an N-channel MOSFET at the power supply voltage Vcc and the ground potential Vss of the circuit, respectively. It is composed of a provided CMOS (complementary MOS) latch circuit, and its pair of input / output nodes is coupled to the complementary data line D. The timing pulse φpa is for controlling the power switch MOSFET. The non-inverting timing pulse φpa and the inverting timing pulse pa are used to control the power switch MOSFET composed of the N-channel MOSFET and the P-channel MOSFET.
In the figure, only the non-inverted timing pulse φpa is shown. The pair of power switch MOSFETs are turned off immediately before the start of the precharge operation. As a result, the complementary data line D, in the floating state, is Vc.
Holds c and Vss levels.

A circuit switch C-SW is a column switch, and the complementary data lines selected in accordance with the column selection signal are common complementary data lines (represented by one line) CD, ▲.
Combine with ▼.

A circuit symbol R-ADB is a row address buffer, which receives external address signals from external terminals A0 to A8 and receives internal complementary address signals a0 to a8,
0 to 8 are formed. In the following description and drawings,
A pair of internal complementary address signals, to be expressed as internal complementary address signal a 0, for example, a0,0. Therefore,
The internal complementary address signals a0 to a8, 0 to 8 are
It represents the internal complementary address signal a 0 to a 8.

A circuit address C-ADB is a column address buffer, which receives external address signals from external terminals A9 to A17 and receives internal complementary address signals a9 to a1.
7, 9 to 17 are formed. In the drawings and the following description, the internal complementary address signals a9-a17, 9-
17 represents the internal complementary address signal a. 9 to a 17.

A circuit symbol R-DCR is a row address decoder, which receives an internal complementary address signal a 0 to a 8 via a multiplexer MPX described later and receives the M-AR.
A Y word line selection signal is formed. This word line selection signal is synchronized with the word line selection timing signal φx in synchronization with M
-Committed to ARY.

A circuit symbol MA indicates a main amplifier, which has a circuit configuration similar to that of the sense amplifier SA.

The circuit symbol DOB is a data output buffer, which sends the read data from the main amplifier MA to the external terminals I / O by the timing pulse rw. When writing, the timing pulse rw
This data output buffer DOB is
It is made inoperative (output high impedance).

A circuit symbol DIB is a data input buffer, which is connected to the external terminal I / by the timing pulse rw.
Write data from O is transmitted to the common complementary data line. At the time of reading, the DIB is made inoperative in the same manner as above by the low level of the timing pulse rw. By this, if necessary, the terminals Dout and Din can be connected to a common external data bus. The terminals Dout and Din may be common terminals.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, what is indicated by the circuit symbol RATD is an address signal change detection circuit which receives the address signals a0 to a8 (or 0 to 8) and detects the rising or falling change thereof. Although not particularly limited, what is indicated by the circuit symbol CATD is the address signal a.
An address signal change detection circuit that receives 9 to a17 (or 9 to 17) and detects the rising or falling change.

The address signal change detection circuit RATD is not particularly limited, but an exclusive OR circuit receiving the address signals a0 to a8 and its delay signal, and an OR circuit receiving output signals of these exclusive OR circuits. Composed of and. That is, an exclusive circuit for receiving the address signal and the delayed signal of the address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of the nine exclusive OR circuits are input to the logical OR circuit. When any one of the address signals a0 to a8 changes, the address signal change detection circuit RATD forms an address signal change detection pulse φr synchronized with the change timing.

The address signal change detection circuit CATD has the same configuration as the address signal change detection circuit RATD. That is, it is composed of an exclusive OR circuit which receives the address signals a9 to a17 and their delayed signals, and an OR circuit which receives the output signals of these exclusive point OR circuits. This address signal change detection circuit C
Similar to the address signal change detection circuit RATD, when any one of the address signals a9 to a17 changes, the ATD forms an address signal change detection pulse φc synchronized with the change timing.

A circuit symbol TG is a timing generation circuit, which forms the main timing signals and the like shown as the representative. That is, the timing generation circuit TG
Receives the address signal change detection pulses φr and φc, the write enable signal ▲ ▼ and the chip selection signal ▲ ▼ supplied from the external terminals, and receives the series of timing pulses and the serial reading of the memory array M-ARY described later. Form the timing pulses required for operation. The timing generation circuit TG has a built-in one-shot pulse generation circuit for automatically setting the level of the complementary data line when the power is turned on, as described later.

A circuit symbol MPX is a multiplexer, and the address buffer R- is supplied in accordance with a control signal (not shown) from an automatic refresh circuit REF described later.
Internal complementary address formed by ADB signal a 0 to a 8
When, the automatic refresh circuit REF formed internal complementary address signal a 0 to a 8 and selectively the decoder R
-Tell the DCR.

The circuit symbol Vbb-G is a substrate bias voltage generating circuit. Substrate bias voltage generator Vbb-G
Is + 5V applied between the power supply terminal Vcc which constitutes the external terminal of the integrated circuit and the reference potential terminal or the ground terminal.
In response to such a positive power supply voltage, a negative back bias voltage -Vbb to be supplied to the semiconductor substrate is generated. This causes a back bias voltage to be applied to the substrate gate of the N-channel MOSFET.

The circuit symbol REF is an automatic refresh circuit, which includes a fresh address counter, a timer, etc., and a refresh signal from an external terminal.
It is activated by setting ▼ to low level. That is, when the refresh signal RESH is set to the low level when the chip selection signal ▲ ▼ is at the high level, the automatic refresh circuit REF switches to the multiplexer MPX and transmits the internal address signal from the built-in refresh address counter to the row decoder R-DCR. Refresh operation (auto refresh) by selecting one word line. Further, when the refresh signal ▲ ▼ is kept at the low level, the timer operates and the refresh address counter is incremented at regular time intervals, during which continuous refresh operation (self-refresh) is performed.

The dynamic RAM of the illustrated block constitutes a pseudo static RAM. Various circuit operations are controlled by detection pulses φr and φc sent from the address signal change detection circuits RATD and CATD.

When the detection pulse φr is output according to the level change in at least one of the row-related internal address signals output from the multiplexer MPX, the timing generation circuit TG responds to the timing for controlling the operation of the row-related circuit. The signal is output. The timing signal φpa is
When the detection pulse φr is generated, the level is set to deactivate the sense amplifier SA accordingly. The timing signal φp is set to, for example, a high level precharge instruction level for a predetermined period from the timing at which the timing signal φpa is changed or at the timing slightly delayed. As a result, the precharge circuit PC is operated and each data line in the memory array M-ARY is precharged to about Vcc / 2 level. That is, the preparation before the data read operation is executed.

The timing signal φx is set to, for example, a low level in synchronization with the detection pulse φr, and is set to a high level after the timing signal φp is set to a low level. Row decoder RD
The CR is operated by setting the timing signal φx to the high level. As a result, the memory array M-AR
One of the plurality of word lines in Y corresponding to the row-system internal address signal is selected.

The timing signal φpa is set to a level for operating the sense amplifier SA after the timing signal φx is set to the high level. This starts amplification of the data read from the memory cells in the memory array M-ARY.

The timing signal φy is set to the low level when the detection pulse φr is generated, and is set to the high level after the timing signals φx and φpa are generated. Timing signal φy
Further, when the detection pulse φc is generated while the timing signal φx is set to the high level, that is, when the row-related address signal is changed, it is set to the low level reset level for a predetermined period from that time and then set to the high level. To be done. The column decoder C-DCR is operated by setting the timing signal φy to the high level. The column switch C-SW is operated by the operation of the column decoder C-DCR. As a result, one of a plurality of pairs of data lines in the memory array M-ARY corresponding to the column address signal is selected.

The timing signal φma is set to the low level in synchronization with the timing signal φy being set to the low level, and is set to the high level after the timing signal φy is set to the high level. The main amplifier MA is operated by setting the timing signal φma to the high level.

The timing signal is set to, for example, a low level when the chip select signal at the external terminal ▲ ▼ is at a low level (selection level) and the write enable signal at the external terminal ▲ ▼ is at a high level (read operation instruction level). It

FIG. 2 shows a circuit diagram of a reference example of an automatic level setting circuit for the complementary data lines in the memory array M-ARY. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. In the figure, unless otherwise specified, an N-channel MOSFET (insulated gate field effect transistor) is used.
Is. The MOSFET with a straight line added between the source and drain is a P-channel MOSFET.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N channel MOS
The FET is a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region and the surface of the semiconductor substrate between the source region and the drain region through a thin gate insulating film. Composed of electrodes. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of Ns formed thereon.
Configure a common substrate gate for channel MOSFETs. The N-type well region constitutes the body gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is
It is coupled to the power supply terminal VCC of FIG.

In FIG. 2, in the memory array M-ARY, two pairs of rows are shown as a representative, and an address selection MOS is provided to each pair of complementary data D, which are arranged in parallel.
Input / output nodes of a plurality of memory cells each composed of the FET Qm and the information storage capacitor Cs are distributed and coupled with a predetermined regularity. MOSFET Qm for address selection of memory cells arranged in the same column
Has its gate coupled to the corresponding word line W.

The precharge circuit PC is a MOSF shown as a representative.
Like ETQ1 and ET2, it is composed of a complementary data line D and a switch MOSFET provided between them. The timing pulse φp is supplied to the gates of these MOSFETs Q1 and Q2.

In this reference example, since the complementary data line D, immediately after the power is turned on, is set to the power supply voltage Vcc and the ground potential Vss of the circuit, one complementary data line D is N-channel MOSFE.
The sources or drains of TQ3 and Q5 are coupled, and the sources or drains of P channel MOSFETs Q4 and Q6 are coupled to the other complementary data line. N channel M above
The other source or drain of the OSFETs Q3 and Q5 is
They are commonly connected to each other and are supplied with a timing signal φ2. The other sources or drains of the P-channel MOSFETs Q4 and Q6 are commonly connected to each other and supplied with the timing signal φ1. N channel MOSFE
The timing signal φ1 is commonly supplied to the gates of TQ3 and Q5, and the P-channel MOSFETs Q4 and Q6 are supplied.
The timing signal φ2 is commonly supplied to the gates of the above.

These timing signals φ1 and φ2 are formed by the following voltage detection circuit. The rising voltage of the power supply voltage Vcc is delayed by the P-channel MOSFET Q7 and the capacitor C. That is, P-channel MOSFET
Q7 acts as a resistance means by constantly supplying the ground potential of the circuit to its gate. This allows
Connection point between MOSFET Q7 and capacitor C (node N
The voltage of 1) gradually rises with a delay with respect to the rise of the power supply voltage Vcc when the power is turned on. This voltage N1 is
On the one hand, it is supplied to one input of a NAND gate circuit G1. On the other hand, the voltage N1 is supplied to the other input of the NAND gate circuit G1 through the delay circuit DL. That is, the output N2 of the delay circuit DL
Is set to a voltage that rises with a delay from the voltage N1.
As a result, the NAND gate circuit G1 has a high level (logic "1") output signal because its input is at a low level (logic "0") equal to or lower than the logic threshold voltage when the power supply voltage Vcc reaches its operating voltage. (Timing signal φ1) is formed. The voltage N1 is first set to a high level equal to or higher than the logic threshold voltage of the NAND gate circuit G1, but the output N2 of the delay circuit DL is still low level equal to or lower than the logic threshold voltage. Then, when the output N2 of the delay circuit DL reaches or exceeds the logic threshold voltage voltage of the NAND gate circuit G1 with a delay, the output of the NAND gate circuit G1 changes from the high level to the low level. This output is sent out as the timing signal φ1 via the inverter circuits IV1 and IV2 in the serial form. Further, the timing signal φ1 is inverted by the inverter circuit IV3, and the timing signal φ1 is inverted.
Sent as 2. The inverter circuits IV2 and IV
3 is a control signal for the MOSFETs Q3 to Q6 for level setting and supplies the level of the complementary data line D, so that the current driving capability thereof is set relatively large.

In this reference example, the timing signal φ1 and its inverted timing signal φ2 which become high level immediately after the power is turned on are formed as described above. The high level of the timing signal φ1 turns on the N-channel MOSFETs Q3 and Q5, and sets the complementary data line D coupled thereto to the low level of the timing signal φ2. Further, depending on the low level of the timing signal φ2, the P channel MOSFE
TQ4 and Q6 are turned on to set the complementary data line D, coupled thereto, to the high level of the timing signal φ1.

When the timing signal φ1 goes low and the timing signal φ2 goes high, the N channel M
OSFET Q3, Q5 and P-channel MOSFET Q
Both 4, Q6 are turned off. As a result, the complementary data line D, holds the low level and the high level in the floating state. After that, when an address signal for a write or read operation is supplied, a timing pulse φp is formed at the change timing, the precharge MSOFETs Q1 and Q2 are turned on, and the complementary data line is short-circuited to cause the complementary data. Line D, about Vcc
Set the precharge level to / 2. As a result, the write or read operation can be started immediately.

A circuit diagram of an embodiment of the present invention is shown in FIG. In this embodiment, the sense amplifier SA is used as the level setting circuit for the complementary data line immediately after the power is turned on. That is, the sense amplifier SA includes P-channel MOSFETs Q11 and Q13 and an N-channel MO.
It is composed of a CMOS latch circuit composed of SFETs Q10 and Q12, and a pair of input / output nodes thereof are coupled to the complementary data line D. The latch circuit is brought into operation by being supplied with the power supply voltage Vcc through the P-channel MOSFET Q19 and the ground voltage Vss of the circuit through the N-channel MOSFET Q18. The other sense amplifier SA is also similar to the above P channel M.
OSFET Q15, Q17 and N-channel MOSFET
It is constituted by a CMOS latch circuit composed of Q14 and Q16, and an operating voltage is commonly supplied through the switch MOSFETs Q19 and Q18.

In the gate of the power switch MOSFET Q18,
Timing pulse φpa 'is supplied, and power switch M
The inverter circuit IV4 is provided at the gate of the OSFET Q19.
The inverted timing pulse pa ′ is supplied via the. This timing pulse φpa ′ is formed by the following circuit.

P channel MO similar to the reference circuit shown in FIG.
One-shot pulse φ1 ′ formed by the SFET Q7, the capacitor C, the delay circuit DL, and the NAND gate circuit G1
Is supplied to one input terminal of the exclusive OR circuit EX. To the other input terminal of the exclusive OR circuit EX,
The operation timing pulse φpa of the sense amplifier is supplied. Then, the timing pulse φpa ′ is formed from the output of the exclusive OR circuit EX.

In this embodiment, immediately after the power is turned on, the operation timing pulse φpa of the sense amplifier is not formed and is at the low level (logic “0”). Therefore, when the timing signal φ1 ′ similar to that shown in FIG. 3 is formed by turning on the power, the timing pulse φpa ′ that becomes high level is formed during the high level (logic “1”) period. It As a result, the N-channel MOSFET Q18 and the P-channel MOSFET Q19 that supply the operating voltage to the CMOS latch circuit are turned on. CM above
The OS latch circuit starts its operation when the operating voltage is supplied, and one of the complementary data lines D is set to the high level,
Set the other to low level. When the timing pulse φpa ′ goes low due to the low level of the timing signal φ1 ′, the power switch MOSFETs Q18, Q
19 is turned off. This allows complementary data lines D,
Holds a high level and a low level in a floating state. The subsequent operation is similar to that of the reference example shown in FIG.

In this embodiment, since the sense amplifier circuit can be used to set the level of the complementary data line D in the memory array M-ARY immediately after power-on, power-on is detected and one shot pulse is generated. The above automatic level setting can be performed by a relatively simple circuit such as a circuit.

In the case of the reference example as shown in FIG. 2, MOSFETs Q3 to Q6 are coupled to the complementary data lines for precharging, and each of the MOSFETs Q3 to Q6 is expected to operate at the same high speed as the static RAM. This is one factor that limits the operating speed of the pseudo-static RAM that should be used. On the other hand, in the case of the embodiment of FIG. 4, since the sense amplifier itself is used as the precharge means, the number of elements can be reduced as compared with that of FIG. 2 and the parasitic capacitance on the complementary data line can be reduced. The size can be reduced and the speed can be increased easily. Further, in the case of the reference example as shown in FIG. 2, the common inverter circuits IV1 and IV2 need to have a large size so as to have a large driving force so that all complementary data lines can be precharged at the same time. is there.
On the other hand, in the case of the embodiment shown in FIG. 4, since the corresponding complementary data lines may be precharged by the respective sense amplifiers, high-speed precharge is possible.

In FIG. 4, the complementary data D, is the column switch MOSFETs Q20, Q21 and Q23, Q2.
4 to a common complementary data line CD, ▲ ▼. These column switch MOSFETs Q20, Q2
The gates of 1 and Q23 and Q24 are commonly supplied with a selection signal formed by the column decoder C-DCR. Such a column selection circuit is omitted in FIG.

[Effect]

(1) The power-on is detected and one shot pulse is generated, whereby the level of the complementary data line in the memory array can be automatically set. Therefore, immediately after power-on, the write or read operation is performed. The effect of being able to do is obtained. In other words, the dummy cycle for setting the level, which is a precondition for the Vcc / 2 precharge on the complementary data line, becomes unnecessary. This makes it possible to realize a pseudo-static RAM that approximates the operation of a static RAM that is easy to handle.

(2) By using the amplification operation of the CMOS latch circuit that configures the sense amplifier for setting the level of the complementary data line, it is possible to realize the above automatic level setting by adding a very simple circuit. can get.

(3) As is well known, the sense amplifier having the CMOS latch circuit configuration has the ability to sufficiently drive its output, that is, complementary data, to the power supply voltage level and the ground potential level. Therefore, the precharge potential of the complementary data line when the precharge circuit (Q1, Q2) is operated is
Precisely Vcc / 2 according to the power supply voltage level and the ground voltage level previously applied to the complementary data line by the CMOS latch circuit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, power supply voltage Vcc
Any circuit may be used as a circuit for detecting the rising edge of the pulse and generating a one-shot pulse.

[Field of application]

The present invention can be widely used for a dynamic RAM in which the peripheral circuit is composed of a static circuit, the memory array is composed of dynamic memory cells, and complementary data lines thereof are precharged to Vcc / 2.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a main part and a reference example, FIG. 3 is a timing chart for explaining its operation, and FIG. FIG. 3 is a schematic circuit diagram showing an embodiment of the present invention. M-ARY ... memory array, PC ... precharge circuit, SA ... sense amplifier, R-ADB ... row address buffer, C-SW ... column switch, C-ADB
...... Column address buffer, R-DCR ... Row address decoder, C-DCR ... Column address decoder, MA ... Main amplifier, RATD, CATD ... Address signal change detection circuit, TG ... Timing generation circuit, REF ... ... automatic refresh circuit, DOB ... data output buffer, DIB ... data input buffer, MP
X: Multiplexer

Claims (1)

[Claims] 1. A memory array in which dynamic memory cells are arranged in a matrix, an external terminal for receiving a row address signal designating one of the memory rows in the memory array, and one of the memory arrays. An external terminal that receives a column address signal that specifies a memory column, a row address selection circuit that receives the row address signal to form a signal for selecting a memory row, and a memory row that receives the column address signal. A column address selection circuit for forming a signal for amplifying a level difference, a plurality of sense amplifiers for amplifying a level difference between complementary data lines forming a pair in the memory array, an address counter, and a control signal from the outside. It is activated to generate an address signal for selecting a word line of any of the memory rows in the memory array. An automatic refresh circuit; an address signal change detection circuit for detecting a change in an address signal input from the external terminal; and a row address selection circuit based on a detection signal from the address signal change detection circuit and an external control signal. A timing generation circuit that generates a timing signal for an internal circuit such as a column address selection circuit, a precharge circuit that is connected between the complementary data lines to precharge by short-circuiting these, and a change in power supply voltage at power-on Is a pseudo-static RAM including a pulse generating circuit for detecting a pulse signal having a predetermined time width, and the sense amplifier is a CMOS latch having a pair of input / output terminals connected to each of the complementary data lines. Supplying power supply voltage and ground potential to the circuit and the CMOS latch circuit The power switch is composed of a pair of power switch MOSFETs, and the power switch is provided by a timing signal obtained by logically synthesizing the pulse signal output from the pulse generation circuit and the operation timing signal of the sense amplifier output from the timing generation circuit in a logic circuit. A pseudo static RAM, which is configured to turn on a MOSFET to operate each sense amplifier.