JPH061454B2 - Communication method between processors - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication method between a plurality of processors, and more particularly to a communication method that enables direct data transfer between tasks between a plurality of processors.

[Conventional technology]

FIG. 4 shows a configuration example of a conventional interprocessor communication system. In FIG. 4, each task 17 in the processors 10, 11, 12 is associated with the sub-channel 16 of the channels 20, 21, 22 in a one-to-one correspondence. On the other hand, the inter-processor connection device 14 uses the channel interface 15 to connect the channels 2 of the processors 10, 11 and 12.
It is connected to 0, 21, 22. The interprocessor connection device 14 has a function of storing a destination processor address, a destination subchannel address, and a path setting state for each subchannel. A plurality of processors are connected to each other via the inter-processor connection device 14 by a transmission path 13 having an arbitrary topology. In addition, each sub-channel is connected one-to-one.

Data transfer between sub-channels is performed by the following procedure.
The inter-processor connection device 14 on the transmission side receives a command for designating a destination address, and sets the destination processor address and the destination sub channel address in the storage area corresponding to the I / O address (the sub channel address). ,
The sub-channel is set to the address setting state. The same address setting is performed in the inter-processor connection device 14 on the receiving side. When a data transfer request occurs, the inter-processor connection device 14 on the transmission side receives a data transfer request from the channel,
The destination processor address and destination subchannel address are read from the storage area corresponding to the designated subchannel address, a transmission frame is assembled, and the data is sent to the transmission path. If the address is not set in storage, it reports an error to the channel. When the inter-processor connection device 14 on the receiving side receives a frame from the transmission path, it checks the status information of the storage area corresponding to the destination sub-channel address specified in the frame, and if it is receivable, the corresponding sub-channel of the channel is checked. Request the channel to receive data. If the reception is impossible, the fact is reported to the sender.

As described above, in the conventional method, the partner processor address and the partner subchannel address are set in advance in one of the storage areas for storing the path setting states of both the transmitting side and the receiving side when the system is started up before data transfer. Need to put. That is, one to one sub-channel pair is set in advance. Therefore, since subchannel pairs are set in advance even for infrequent communications such as broadcast communication and datagram communication for data circulation, the use of subchannel pairs is inefficient, and there is a shortage of subchannel pairs. There are some drawbacks.

[Object of the Invention] An object of the present invention is to effectively use a limited number of sub-channels in a communication system between a plurality of processors, and to prepare for data reception at a receiving side HOST in datagram communication in advance. Is to be able to do it.

[Differences Between Features of Invention and Prior Art]

The present invention is a mode in which, in addition to the conventional data transfer mode in which a fixed one-to-one sub-channel pair is set in advance (fixed partner mode), a sub-channel pair is set and released each time data is transferred to perform data transfer. (Opposite floating mode) is provided. Each sub-channel is preset to one of these two types of modes, and communication is performed by selecting the mode.

The fixed channel sub-channel is set in advance by the inter-processor connection device on the transmitting side and the receiving side, but the floating channel sub-channel is set on the transmitting side and the receiving side at system startup. A sub-channel pair (path) is not set, and each time data is transferred, it is set in the path setting state storage area by a command in the inter-processor connection device on the transmitting side, and then data is immediately transmitted. The inter-processor connection device on the data receiving side looks at the sub-channel used from the received frame, and in the case of the partner floating mode, at the time of data reception, the path check based on the contents of the path setting state storage area (specified source Other than the sub-channel address is rejected.), The path is set based on the address information of the received frame, and the path information (source address, source sub-channel address) is set by the read path information command (RP command) from the processor. To the processor. Then, the received data is sent to the processor by the read command from the processor.

This is different from the conventional technique in that there is a mode in which path setting is not performed in advance at system startup and path setting is performed during data transfer.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention. The basic structure is the same as that shown in FIG.
-5 is not fixedly coupled to the other sub-channel 16-1 in a one-to-one manner, but is allowed to be coupled to another sub-channel 16-10 at the end of data transfer.
Therefore, the interprocessor coupling device 14 has the following functions.

When starting the system, each sub-channel is assigned to fixed partner mode and partner floating mode.

The partner subchannel is written in the storage area of the subchannel in the partner fixed mode, and a subchannel pair is set in advance. This setting is not performed for the sub-channel in the partner floating mode.

The data transfer operation function in the fixed partner mode is as conventional.

The data transfer operation function in the partner floating mode is as follows.

I. When a data transfer request occurs, first receive a command to set the destination address, set the destination processor address and destination subchannel in the memory area corresponding to the I / O address (subchannel address), and set the corresponding subchannel. Enter the address setting state.

B. When a data transfer request is received from the channel, the destination address and destination subchannel address are read from the storage area corresponding to the designated subchannel address, and WR
An IRE request transmission frame is assembled and the data is transmitted to the transmission line.

C. When a WRITE request frame is received from the transmission line,
The status information of the storage area corresponding to the destination subchannel address specified in the frame is checked and the status is RE
If it is AD display and the subchannel is not in use and can be received, the source processor address and the source subchannel address are written in the storage area, and a frame for sending a synchronization notification to the source is sent to the transmission path. . If the sub-channel is in use, the fact is reported to the transmission source.

D. When the synchronization frame is received from the transmission line, the channel is requested to send data, the data is framed and sent to the transmission line.

E. When the data frame is received from the transmission path, the subchannel corresponding to the channel is requested to receive the path information (source processor address, source subchannel address). After receiving the path information, the sub-channel of the channel is requested to receive data.

FIG. 2 shows an embodiment of an interprocessor connection device to which the present invention is applied, which is an I / O interface control unit 201, an input / output data (IOD) register 202, a command (CM).
D) register 203, device status (DSB) register 204, device control unit 205, sub-channel table 20
6, a data link control unit 208, an instruction (IR) register 209, a data buffer 210, a report (SR) register 211, and the like. Subchannel table 206
Stores a partner processor address (DPCI) for setting a communication path, a partner subchannel address (DSBC), and the path setting status (STA) for each subchannel of the channel connected to the interprocessor connection device. Has an area to

Hereinafter, the transfer operation will be described based on the communication example of FIG. 3 with a focus on FIG. An example of data transfer operation in fixed partner mode is
Since it is the same as the conventional method, only the case of the partner floating mode will be explained here. Incidentally, in FIG. 3, the HOS at the left end
T is the processor 10 in FIG. 1, and RCI # A is the inter-processor connection device 14 connected to the processor 10.
Also, the HOST at the right end is the processor 11 of FIG.
RCT # B corresponds to the inter-processor connection device 14 connected to the processor 11.

The inter-processor connection device PCI # A that has received a path setting command (for example, a SET command) for the I / O address # 1 (subchannel address #i) from the HOST,
When the I / O interface controller 201 knows that the I / O address and the operation command have been sent from the channel, the I / O address #i is stored in the IOD register 202.
The operation command SET is set in the CMD register 223, and the activation result is set in the DSB register 204 and reported to the channel. When the destination processor address (DPCI) #B and the sub channel address (DSBC) #j are continuously sent from the channel, the device control unit 205 receives the sub channel table 206 designated by the IOD register 202.
When the destination addresses #B and #j and the path setting display are set to the sub-channel #i of the
Channel end (CE) and device end (DE) are set in the B register 204, and it is reported to the channel that the path setting operation has been completed normally.

Then, the transfer operation command is given. It is assumed that the data is transferred from PCI #A to PCI #B. H on the PCI # B side
The task on the OST processor issues an advance read command of the RP command (path information read command) to all the sub-channels, and the task of the HOST processor on the PCI #A side changes to the corresponding sub-channels when the transfer request occurs. Make a write request for a WRITE command. Pre-reading is performed as follows for all sub-channels by multiple processing. When a certain RP command is issued,
The RP command is entered in the CMD register 203 of PCI # B, and the designated sub-channel address is set in the IOD register 202. FIG. 3 shows a case where the sub-channel address #j is designated. Device control unit 20
5 is a status area (ST) of the corresponding subchannel #j of the subchannel table 206 designated by the IOD register 202.
A) Set that 207 had a READ request, and set DS
A command retry request (RET) display (SM, CE, UC) is displayed in the B register 204, and the I / O interface control unit 201 is instructed to perform the reporting operation.

On the other hand, when a WRITE command is issued to PCI # A, the WRITE is sent to the CMD register 203 in the same manner as above.
TE and #i are set in the IOD register 202. The device control unit 205 informs the IO that the WRITE request has been made.
Subchannel table 2 specified by D register 202
When it is registered in the corresponding sub-channel #i of 06, the WRI is written in the instruction register 209 to the data link control unit 208.
Set TE request. The data link control unit 208 assembles the transmission request frame 301 shown in FIG. 3 based on the information in the instruction register 209, the IOD register 202, and the sub-channel table 206, and sends it to the loop transmission line 13. The command retry request (RET) display (SM, CE, UC) is displayed on the I / O
The interface control unit 201 is instructed to perform the reporting operation.

Upon receiving the transmission request frame 301, the data link control unit 208 of PCI # B sends the frame to the data buffer 2
10 and buffer the destination sub-channel address #j in the frame in the IOD register 202 and WRI.
Place the TE request in the report register 211. Device control unit 2
05 confirms that the sub-channel address specified by the IOD register 202 is in the floating mode, and checks the sub-channel without performing a path check (whether the sub-channel of the sub-channel table 206 is written). When it is confirmed that the status information registered in the status area (STA) of the corresponding sub-channel #j of the channel table 206 can be received by READ display, the transmission source processor address #A and the sub-channel address #i are set as sub-addresses. In order to write to the sub-channel #j of the channel table 206, to notify the other processor of the data transmission request, the instruction register 209 is synchronously displayed (M), and the synchronous report frame 302 of FIG. 3 is sent to PCI #A. The data link control unit 208 is instructed to do so. The data link control unit 208 requests the transfer control unit 212 for data required for frame construction, and sends the data to the loop transmission line 13 while assembling the frame.

Upon receiving the synchronization frame, the data link control unit 208 of PCI #A buffers the frame in the data buffer 210, reports the destination subchannel address #i in the frame to the IOD register 202, and reports synchronization indication (M). Set in the register 211. Since the device control unit 205 reports to the own processor that the synchronization report has been received,
Set device end (DE) to B register 204
Instructs the / O interface control unit 201 to perform a reporting operation. Upon completion of the de-high speed (DE), a command retry instruction is issued from the channel to PCI # A, and WRIT
E command is sent. The PCI # A I / O interface control unit 201 sets the WRITE command and IOD address #i sent by the command retry in the CMD register 203 and the IOD register 202. The device control unit 205 checks the STA 207 of the corresponding sub-channel #i of the sub-channel table 206 specified by the IOD register 202, and if the path is set and the synchronization is completed in the WRITE system, the activation is started. The DSB register 204 indicates that the operation was successful.
Set all "0" to I / O interface controller 2
01 is instructed to perform a reporting operation, and the process proceeds to transfer of WRITE data. The transfer control unit 212 buffers the data sent from the channel in the data buffer 210. Further, the data ring control unit 208 uses the instruction register 2
09, IOD register 202, sub-channel table 2
06, information of the data buffer 210 is used to assemble the data frame 303 shown in FIG.
Send to 3.

Upon receiving the data frame 303 from the loop transmission line 16, the data link control unit 208 of PCI #B sets the transmission destination sub-channel address #j of the frame to the IOD register 2
In 02, the data transfer is set in the report register 211, and the received frame is buffered in the data buffer 210. The device control unit 205 uses the IOD register 20.
2 checks the corresponding sub-channel #j of the sub-channel table 206 designated by 2 and its status area (STA) 2
If the path setting display, the READ system, and the synchronization completion display are displayed in 07 and the source processor address #A and the sub channel address #i match those specified in the received frame, the RP command restart (retry) is performed. Device end (DE) is displayed on the DSB register 204 and the I / O interface control unit 201 is instructed to perform a reporting operation. Upon device end (DE), a command retry instruction is issued from the channel to PCI # B, and R
P command is sent. The PCI #B I / O interface control unit 201 sets the command and IOD address #j sent by the command retry in the CMD register 203 and the IOD register 202. The device control unit 205 uses the STA2 of the corresponding subchannel #j of the subchannel table 206 designated by the IOD register 202.
Check 07, the path is set, READ
When synchronization is completed in the system, it indicates that the startup has been normally performed. Therefore, all "0" is set in the DSB register 204 to instruct the I / O interface control unit 201 to perform the startup report operation, Move to information reading operation. After the read operation is completed, the channel end (DE) and device end (DE) are written to the DSB register 204 to report the normal end.
The display is performed and the I / O interface control unit 201 is instructed to perform the reporting operation.

Next, a READ command is sent from the PCI # B channel that has received CE and DE. REA command is P
When entering CI # B, the CMD register 203 of PDI # B
This command is entered in and the designated register address #j is set in the IOD register 202. Device control unit 205
Indicates that the activation is normally performed, all "0" is set in the DSB register 204 to instruct the I / O interface control unit 201 to perform the activation reporting operation, and the operation shifts to the READ operation of the reception data. After the transfer operation is completed, CE and DE are displayed in the DSB register 204 to report the normal end, and the I / O interface control unit 201 is instructed to perform the report operation. At the same time, the device control unit 205 displays ACK in the instruction register 209 in order to report to the partner processor that data has been normally received, and the data link control unit 208 causes the ACK frame 304 shown in FIG.
To send to the other processor. Then, the contents of the corresponding address part #j of the sub-channel table 206 are returned to the initial state.

When the PCI # A also receives the ACK frame 304 from the PCI # B after transmitting the data, the device control unit 205 checks whether the contents of the IOD register 202 and the transmission destination address of the reception ACK frame 303 match. If the addresses match and the content of the report register 211 set from the ACK frame ends normally, the DSB register 20
CE and DE are set in 4, and the I / O interface control unit 201 is instructed to perform a reporting operation. Also, the state of the corresponding address #i in the sub-channel table 206 is returned to the initial state.

Although a loop-shaped transmission line has been described as an example of this system here, any tobology transmission line such as a bus type or a star type can be applied.

〔The invention's effect〕

As described above, according to the present invention, in addition to a mode in which a path is set in advance at system startup and data transfer is performed, a mode in which a path is set at data transfer without performing path setting at system startup in advance is also provided. The advantage is that the limited number of sub-channels can be effectively used and sub-channels can be effectively used for temporary communication such as broadcast communication and datagram communication, and the receiving side can receive data. Since the HOST can know the path information before the start, there is an advantage that the reception data storage area can be allocated in advance on the HOST side and the preparation for reception is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an interprocessor communication system according to the present invention, FIG. 2 is a detailed diagram of an interprocessor connection device in FIG. 1, and FIG. 3 is a diagram showing a communication example according to the present invention system. FIG. 4 is a diagram showing a configuration example of a conventional interprocessor communication system. 10, 11, 12 ... Processor, 20, 21, 22 ... Channel, 13 ... Transmission path, 14 ... Inter-processor connection device, 16 ... Sub-channel, 17 ... Task.

Claims (1)

[Claims] 1. An information processing system in which a plurality of processors are interconnected by a transmission line, wherein an interprocessor connection device is installed between the processor and the transmission line, and the processor input / output of the processor is provided in the interprocessor connection device. Storage means for storing a destination processor address, a destination subchannel address, and the bus setting state for setting a communication path corresponding to the subchannel of the channel that controls the operation;
A means for designating a mode in which a pair of fixed sub-channels of pair 1 are used for communication (hereinafter referred to as partner fixed mode) and a mode for communicating with an arbitrary partner sub-channel (hereinafter referred to as partner floating mode), and a partner floating mode And a means for receiving a transfer request from the channel to a certain sub-channel, setting a destination processor address and a destination sub-channel address in the corresponding sub-channel of the storage means, and assembling a transmission frame based on the information in the storage means. ,
A means for sending to the transmission path and a frame for receiving the frame from the transmission path, setting the source processor address and the source subchannel address specified in the frame in the storage means, and notifying the source of synchronization. Means for sending to the transmission path, a means for receiving a synchronization frame from the transmission path, requesting data transmission to the channel in response to this, and sending out a transmission data frame to the transmission path, and receiving data from the transmission path, Immediately after receiving the first data frame, means for transmitting the source processor address and the source subchannel address in the subchannel stored in the path setting state to the subchannel in the channel specified in the frame; Means for transmitting a received data frame to a sub-channel within a channel specified in Support inter-communication system.