JPH061809B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor integrated circuit incorporating a resistance element by an ion implantation method, which facilitates h _FE control of an NPN transistor.

(B) Conventional Technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base / emitter is double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are indispensable steps, and a high-concentration buried layer forming step for reducing collector series resistance, an epitaxial layer growing step, and junction separation for each element. This is a step (basic step) essential for manufacturing a bipolar IC along with the isolation region forming step, the electrode forming step for electrical connection, and the like.

On the other hand, there is a demand for incorporating other elements such as a PNP transistor, a resistor, a capacitor, and a Zener diode on the same substrate in view of circuit requirements. In this case, needless to say, it is preferable to divert the basic process as much as possible from the viewpoint of simplifying the process. However, in the base and emitter diffusion process, since various conditions are set with the characteristics of the NPN transistor as the most important factor, integration is often difficult only by the basic process. So, basic NP
A new process may be added for the purpose of incorporating another element or improving the characteristics of another element without forming the N-transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of the base region, and an implantation process. A resistance forming step, a nitride film forming step for forming a nitride film capacitor that can provide a larger capacity than that of a MOS type, and a collector low resistance region forming step for further reducing the collector series resistance of an NPN transistor are all included in it. This is a process (optional process) in which it is determined whether or not to add the bipolar IC by considering the use and purpose and cost of the bipolar IC.

FIG. 3 shows the implantation resistance formed by using the above-mentioned optional process. In the figure, (1) is a P-type semiconductor substrate,
(2) is an N ⁺ type buried layer, (3) is an N type epitaxial layer, (4) is a P ⁺ type isolation region, (5) is an island, (6) is a P type base region of an NPN transistor, (7) ) And (8) are N ⁺ type emitter and collector contact regions of the NPN transistor, (9) is a resistance region by ion implantation, and (10) is a contact region formed by base diffusion.

And, the implantation resistance of FIG. 3 is, for example, Japanese Patent Publication No. 57-2.
It was formed after the emitter diffusion as described in Japanese Patent No. 182.

(C) Problems to be solved by the invention However, when the resistance region (9) is formed after the emitter region (7) is formed, h _FE (current amplification factor) of the NPN transistor is increased.
The heat treatment for controlling the temperature must be performed after forming the resistance region (9). Then, a heat treatment of several hundreds of degrees C. before the photo-etching of the resistance region (9) diffuses the emitter region (7), so that there is a large variation in h _FE of the NPN transistor, which is difficult to control.

Also, the emitter area depends on whether or not the implantation resistance is added.
Since it is necessary to change the heat treatment condition of (7), it is necessary to manage the process for each model, and there is a drawback that the management cannot be standardized.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the resistance region (28) and the base region (29) of the NPN transistor are formed using the first resist pattern (27). A step of ion-implanting boron (B) to be formed, a second resist pattern (27) is formed, and the first resist pattern (27) is used to again implant boron (B) in the base region (29) of the NPN transistor. And the step of ion-implanting the N-type impurity and, after forming the emitter region (33) by selectively diffusing the N-type impurity, heat treatment for controlling h _{FE of the} NPN transistor is performed.

(E) Function According to the present invention, since the emitter diffusion of the NPN transistor is performed after forming the resistance region (28) by ion implantation, extra heat treatment after the formation of the emitter region (33) can be removed.

In addition, since the second ion implantation is performed using the first resist pattern (27) as it is, the photoetching process can be simplified and the base region (29) can be controlled with high accuracy.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (2
The surface of 1) is selectively doped with N-type impurities such as antimony (Sb) or arsenic (As) to form an N ⁺ -type buried layer (22).
(21) N-type epitaxial layer (2
3) is laminated.

Next, as shown in FIG. 1B, the buried layer is formed by selectively diffusing boron (B) from the surface of the epitaxial layer (22).
P ⁺ -type isolation regions (24) are formed so as to surround the (22) and penetrate the epitaxial layer (23). The epitaxial layer (23) surrounded by the isolation region (24) becomes an island (25) for forming each circuit element.

Next, as shown in FIG. 1C, thermal oxidation is performed to form an oxide film (26) on the entire surface of the epitaxial layer (23), and a positive photoresist is applied on the oxide film (26) by spin-on coating.
Subsequently, 1 μm such as reflection type projection system or reduced projection exposure system
A resist pattern (27) for the first time is formed by baking and developing a pattern having a desired shape using an exposure apparatus having the following overlay accuracy.

Next, as shown in FIG. 1D, an oxide film (26) pattern corresponding to the first resist pattern (27) is obtained by anisotropically etching the oxide film (26) by dry etching such as reactive ion etching. Is formed, and then the first ion implantation of boron (B) is performed from the surface of the epitaxial layer (23) with the resist pattern (27) being removed or left to be the same on the two islands (25) surfaces. A resistance region (28) having the impurity concentration of and a base region (29) of the NPN transistor are formed respectively. In the first ion implantation, the dose amount of boron (B) and the accelerating voltage are selected according to the impurity concentration of the resistance region (28) on the side of increasing the specific resistance.

Next, as shown in FIG. 1E, the first resist pattern (2
A second type of resist pattern is formed by spin-on coating a negative photoresist film on the surface with 7) removed or left, and then baking and developing a pattern of a desired shape by proximity exposure method or projection exposure method.
Form (30). The second resist pattern (30) has a smaller shielding area than the first resist pattern (27),
The opening portion of the oxide film (26) pattern is enlarged and opened from the previous pattern. Therefore, the second resist pattern (3
The surface of the region where ions are implanted in the previous step and the edge portion of the first resist pattern (27) or the oxide film (26) pattern are exposed in the opening portion of (0). A part (31) of the second resist pattern (30) directly covers the surface of the resistance region (28) excluding both ends and exposes only the contact portion of the resistance region (28).

Next, as shown in FIG. 1F, using the first resist pattern (27) or oxide film (26) pattern formed in the previous step from the surface of the epitaxial layer (23) as a mask again, the second boron (B) ion is used. Make an injection. Since boron (B) is ion-implanted in the base region (29) of the NPN transistor, the side where the specific resistance is lowered at this stage, that is, the base region (29).
The dose amount of the second ion implantation is set so as to determine the impurity concentration of. In addition, the impurity concentration of the base region (29) is set so that ohmic contact with an electrode to be formed later can be made, and the impurity concentration of the source region (28) is also set to 2 at both ends.
By performing the ion implantation a second time, the contact region (3) for disposing the electrode having the same impurity concentration as the base region (29) is formed.
2) is formed. Resistance area (28) between contact areas (32)
Is covered with a part (31) of the second resist pattern (30), so that the second boron (B) is not ion-implanted. Therefore, the impurity concentration of the portion covered by the part (31) of the second resist pattern (30) remains the impurity concentration set by the first ion implantation, and this region substantially reduces the resistance value of the implantation resistance. It becomes the area to be decided. Further, since the impurity concentration is low, the above-mentioned contact region (32) is required. 1st and 2nd resist pattern (27)
(30) is removed, the whole is covered with a CVD oxide film (26), and heat treatment is performed to diffuse the base region (29) to a certain depth.

In the second ion implantation step, the presence or absence of the first resist pattern (27) does not matter, but if it is left, the advantage of omitting the etching process once and the thickness of the oxide film (26) can be reduced. Have advantages.

Next, as shown in FIG. 1G, the oxide film (26) on the surface of the base region (29) and the surface of the island (25) of the NPN transistor is opened, and phosphorus (P) is used as a mask with the oxide film (26). Immediately after depositing and removing the glass film, heat treatment in an oxidizing or non-oxidizing atmosphere is performed, and phosphorus (P) is driven in to form the emitter region (33) and collector contact region (34) of the NPN transistor. To do. Drive-in of this process controls _hFE (current amplification factor) of NPN transistor.

Next, as shown in FIG. 1H, a predetermined portion of the oxide film (26) is opened by etching to form a contact hole, and then an aluminum layer is formed on the entire surface of the epitaxial layer (23) by a known vapor deposition or sputtering technique. By patterning this aluminum layer, an electrode (35) is provided on each region.

A plan view of the implantation resistor formed by the above-described manufacturing method is as shown in FIG. In the figure, (25) is an island,
(28) shows a resistance region, (32) shows a contact region, (36) shows a contact hole, and (31) shows the shape of a part of the second resist pattern (30) in FIG. 1E. Resistance area (28)
Since the line width and the size of the contact region (32) are already determined by the first resist pattern (27) in FIG. 1C, the resistance value of the implantation resistance is not the distance between the contact regions (32). Part of the second resist pattern (30) (3
It is determined by the length of the resistance area (28) covered by 1). Therefore, in the present embodiment, the size of the contact hole (36) is set to be equal to or smaller than the line width of the resistance region (28), so that the structure in which the change in the resistance value due to the change in the impurity concentration in the contact region (32) is the smallest With this structure, the side end portion (37) of the part (31) of the second resist pattern (30) is connected to the side end portion (3) of the contact region (32).
Matched with 8). Therefore, the occupied area of the implantation resistance can be minimized, the variation of the resistance value due to the mask shift can be neglected, and the base region (29) can be manufactured with the same high precision as the implantation resistance.

According to the above-described manufacturing method of the present application, since the resistance region (28) is formed by ion implantation before the emitter region (33) is formed, the phosphorus (P) for forming the emitter region (33) is deposited. It is possible to immediately shift to drive-in for _hFE control of the NPN transistor without arranging extra heat treatment. Therefore, the NPN transistor h _FE
There is little variation in (current amplification factor), and the difficulty of h _FE control due to the incorporation of implanter resistance can be solved. Further, since the heat treatment conditions for the emitter region (33) can be unified regardless of whether or not the implantation resistance is incorporated, the process control for each model becomes easy.

Further, in the present application, the base region (29) is also formed by ion implantation, and the base region (29) can be formed with the same photoetching precision as that of the resistance region (28), so that the controllability is extremely excellent. Moreover, the resistance region (2
Since 8) and the base region 29 are formed at the same time, the process can be simplified and a highly accurate process can be done only once.

(G) Effect of the Invention As described above, according to the present invention, there is little variation in h _FE of the NPN transistor due to the addition of the implanter resistor as an optional device, and it is extremely easy to control the h _FE of the NPN transistor. There is an advantage that a method of manufacturing an integrated circuit can be provided. Also, since the heat treatment conditions for the emitter region (33) can be unified, the process control for each model can be simplified, and moreover, it is possible to perform multi-model small-quantity production such as heat treating different wafer types in the same diffusion furnace. It also has the advantage that

Furthermore, according to the present application, the resistance region (28) and the base region (2
Since 9) is formed simultaneously, the process can be simplified, and the base region (29) can be formed with the same high precision as the resistance region (28), and moreover, high precision photoetching can be performed only once. Therefore, there is an advantage that a method of manufacturing a semiconductor device in which the controllability of the NPN transistor is further excellent can be provided by the positive controllability of the emitter region 33 and the controllability of the base region 29.

[Brief description of drawings]

1A to 1H are sectional views for explaining the present invention, FIG. 2 is a plan view for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example. . (21) is a P-type semiconductor substrate, (27) is a first resist pattern, (28) is a resistance region, (29) is a base region, (30) is a second resist pattern, and (33) is an emitter region.

Claims (1)

[Claims] 1. A step of forming a plurality of buried layers on the surface of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of an opposite conductivity type on the substrate, and a step of separating the epitaxial layer into a plurality of layers. Forming an island, applying a photoresist on the insulating film on the surface of the epitaxial layer, and forming a base region of a transistor on the surface of the first island; a resistance portion on the second island and the resistance portion; Forming a first resist pattern having an opening for forming a resistance element having contact portions at both ends; selectively removing the insulating film by the first resist pattern; From the top, the first ion implantation of a dose amount that determines the specific resistance of the resistance element is performed to remove impurities of one conductivity type from the transistor. Implanting ions into both the source region and the entire surface of the resistance element; applying photoresist again on the first resist pattern to form a second resist pattern covering the resistance portion of the resistance region; Performing a second ion implantation of a dose from the top of the epitaxial layer that is added to the dose of the first ion implantation to determine the resistivity of the base region of the transistor;
Ion-implanting impurities of one conductivity type into the base region of the transistor and the contact portion of the resistance element; simultaneously removing the first resist pattern and the second resist pattern; the first and second And a step of simultaneously forming the base region of the transistor and the resistance element by thermally diffusing the impurity implanted by ion implantation.