JPH061810B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which a resistance element by an ion implantation method and a MIS type capacitance element, which facilitates h _FE control of an NPN transistor, are incorporated. It relates to a manufacturing method.

(B) Conventional Technology A bipolar IC is mainly composed of a vertical NPN transistor in which a base / emitter is double-diffused on the surface of a semiconductor layer serving as a collector. Therefore, the base and emitter diffusion steps for manufacturing the NPN transistor are indispensable steps, and a high-concentration buried layer forming step for reducing collector series resistance, an epitaxial layer growing step, and junction separation for each element. This is a step (basic step) essential for manufacturing a bipolar IC along with the isolation region forming step, the electrode forming step for electrical connection, and the like.

On the other hand, there is a demand for incorporating other elements such as a PNP transistor, a resistor, a capacitor, and a Zener diode on the same substrate in view of circuit requirements. In this case, needless to say, it is preferable to divert the basic process as much as possible from the viewpoint of simplifying the process. However, in the base and emitter diffusion process, since various conditions are set with the characteristics of the NPN transistor as the most important factor, integration is often difficult only by the basic process. So, basic NP
A new process may be added for the purpose of incorporating another element or improving the characteristics of another element without forming the N-transistor. For example, a P ⁺ diffusion process for forming an anode region for controlling the Zener voltage of a Zener diode with the cathode region by the emitter diffusion, an R diffusion process for forming a resistance region having a specific resistance different from that of the base region, and an implantation process. A resistance forming step, a nitride film forming step for forming a nitride film capacitor that can provide a larger capacity than that of a MOS type, and a collector low resistance region forming step for further reducing the collector series resistance of an NPN transistor are all included in it. This is a process (optional process) in which it is determined whether or not to add the bipolar IC by considering the use and purpose and cost of the bipolar IC.

FIG. 4 shows an example of a conventional semiconductor integrated circuit formed by using the above optional process. In the figure, (1) is P
Type substrate, (2) N type epitaxial layer, (3) N ⁺ type buried layer, (4) P ⁺ type isolation region, (5) island, (6) NP
P type base region of N transistor, (7) N ⁺ type emitter region, (8) N ⁺ type collector contact region, (9) P type resistance region of resistance element, (10) resistance region (9 ) Contact region, (11) is N ^{+ of} MIS type capacitance due to emitter diffusion
The mold lower electrode region, (12) is a silicon nitride film (Si ₃ N ₄ ) as a dielectric thin film, (13) is an oxide film, (14) is an upper electrode, and (15) is an electrode. An MIS type capacitor using a nitride film is described in, for example, Japanese Patent Laid-Open No. 60-244056, and a resistance element using ion implantation is disclosed in, for example, Japanese Patent Publication No. 57-2182.
It is described in Japanese Patent Publication No.

Since the MIS type capacitor uses the lower electrode region (11) by emitter diffusion, the step of forming the dielectric thin film (12) must be performed after the step of depositing the N type impurities forming the emitter region (7). I have to. Further, the resistance region (9) by ion implantation was also performed after the emitter diffusion as described in the above publication.

(C) invention Problems to be Solved by the Invention However, the conventional semiconductor integrated circuit for performing some steps to emitter diffusion after, the NPN transistor h _FE
A final heat treatment for control must be placed after any of the above steps. Then, the phosphor used for the heat treatment or the emitter region (7) formation used in any of the above steps is formed.
The heat treatment performed immediately after depositing (P) once diffuses the phosphorus (P) for forming the emitter region (7), so that the h _FE (current amplification factor) of the NPN transistor varies widely, and its control is difficult. was there. The heat treatment used in any of the above steps is a silicon nitride film (Si ₃ N ₄ )
There is a heat treatment at about 800 ° C. by CVD when depositing the.

In addition, since it is necessary to change the drive-in conditions of the emitter region (7) depending on whether an optional process for incorporating a MIS type capacitance and a resistance element by ion implantation is added, process control for each model is required, There was a drawback that could not be realized.

(D) Means for Solving the Problems The present application has been made in view of the above drawbacks, and a step of forming a lower electrode region (28) of a MIS type capacitor and a resistance region (30) by ion implantation prior to emitter diffusion. And a step of selectively diffusing (depositing) N-type impurities forming the emitter region (36) on the surface of the base region (31), and immediately diffusing the emitter region (36) to a predetermined depth after depositing the N-type impurities. It is characterized in that _hFE of the NPN transistor is controlled by (drive-in).

(E) Function According to the present invention, since the heat treatment for incorporating the poption device is completed prior to the emitter diffusion, any extra heat treatment from the deposit of the emitter region (36) to the drive-in is eliminated. can do.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, a P-type silicon semiconductor substrate (2
N ⁺ -type buried layer (22) formed by selectively doping the N-type impurity of antimony (Sb) or arsenic (As) or the like on the surface of 1), the substrate surrounding the buried layer (22) ( 21) Boron (B) on the surface
Is doped to form a lower diffusion layer (23) which is vertically separated. After that, a thickness of 5 is formed on the entire surface of the substrate (21) by a known vapor deposition method.
An N-type epitaxial layer (24) of 10 μm is laminated.

Next, as shown in FIG. 1B, boron (B) is selectively diffused from the surface of the epitaxial layer (24) to form the epitaxial layer (24).
A plurality of islands (25) are formed by separating the junctions. (26) is an upper diffusion layer that is separated into upper and lower parts, and (27) is an oxide film.

At the same time, by using the diffusion process of the upper diffusion layer 26, M
A lower electrode region (28) to be the lower electrode of the IS type capacitor is formed. According to the present embodiment, the steps can be shared, so that the steps can be simplified. Needless to say, the P ⁺ type diffusion region may be formed alone or by utilizing the process for forming the anode of the Zener diode, or may be formed before or after the subsequent base diffusion process. Further, regardless of the diffusion depth of the lower electrode region (28),
It is desirable that the impurity concentration is a high impurity concentration, for example, 10 ¹⁸ atoms · cm ⁻² or more in view of the hysteresis of the MIS-type capacitance.

Next, as shown in FIG. 1C, a positive or negative first resist pattern (29) is formed on the surface of the epitaxial layer (24), and an oxide film (27) on the surface of the epitaxial layer (24) is formed by dry or wet etching. To open a hole. After that, the epitaxial layer with the first resist pattern (29) left
(24) By implanting boron (B) from the surface,
A resistance region (30) having the same impurity concentration on the surfaces of two islands (25) and a base region (31) of an NPN transistor.
Are formed respectively. The first ion implantation is performed on the side where the specific resistance is increased, that is, according to the impurity concentration in the resistance region (30),
Set the dose amount and acceleration voltage of (B). The heat treatment (drive-in) of the impurities ion-implanted in the first time is not performed at this stage.

Next, as shown in FIG. 1D, the first resist pattern (2
A negative photoresist film is spin-on coated on the surface with 9) removed or left to form a second resist pattern (32). The second resist pattern (32) is 1
The shielding portion is made smaller than the resist pattern (29) of the first time, and the opening portion of the oxide film (27) pattern is enlarged and opened as compared with the previous pattern. Therefore, the surface of the region where the ions were implanted in the previous step and the edge of the first resist pattern (29) or the oxide film (27) pattern should be exposed in the opening of the second resist pattern (32). become. A part (33) of the second resist pattern (32) directly covers the surface of the resistance region (30) excluding both ends and exposes only the contact portion of the resistance region (30).

Then, using the first resist pattern (29) or oxide film (27) pattern formed in the previous step from the surface of the epitaxial layer (24) as a mask again, the second boron (B) ion implantation is performed. Since boron (B) is superimposed and ion-implanted in the base region (31) of the NPN transistor, the second ion-implantation is performed so that the impurity concentration of the side where the specific resistance is lowered, that is, the base region (31) is determined at this stage. The dose amount is set.
The impurity concentration of the base region (31) is set so that ohmic contact with an electrode to be formed later can be performed, and the second region is also ion-implanted at both ends of the resistance region (30). A contact region (34) for electrode disposition having the same impurity concentration as (31) is formed. Since the resistance region (30) between the contact regions (34) is covered with a part (33) of the second resist pattern (32), the second boron (B) is not ion-implanted. Therefore, the impurity concentration of the portion covered with the part (33) of the second resist pattern (32) remains the impurity concentration set by the first ion implantation, and this region substantially has the resistance value of the implantation resistance. It becomes the area to be decided. Further, since the impurity concentration is low, the above-mentioned contact region (34) is required. Then 1
The second and second resist patterns (29) and (32) are removed, the whole is covered with a CVD oxide film (27), and heat treatment is performed in the first and second times to diffuse the ion-implanted impurities to a certain depth. Thus, a base region (31) having a predetermined depth is formed.

Although the presence or absence of the first resist pattern (29) may be used in the second ion implantation step, if it is left, the advantage of omitting the etching process once and the thickness of the oxide film (27) can be reduced. Have advantages. Also, the resistance region (30) and the base region
The formation of (31) may be performed in a single process. Further, by diffusing boron (B) also on the surface of the lower electrode region (28) at the same time as the base diffusion, the surface concentration of the lower electrode region (28) can be improved.

Next, as shown in FIG. 1E, the oxide film (27) on the surface of the epitaxial layer (24) is selectively removed by etching to remove the lower electrode region.
(28) Part of the surface is exposed, and a silicon nitride film (Si ₃ N ₄ ) having a film thickness of several hundreds to several thousand hundreds A is deposited on the entire surface of the epitaxial layer (24) by using a technique such as atmospheric pressure CVD. .. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, it is possible to form a large capacity. Then, a known resist pattern is formed on the surface of the silicon nitride film, and the exposed lower electrode region (28) is formed by using a technique such as dry etching.
A dielectric thin film (35) covering the surface of the is formed. Then, an oxide film (27) is deposited by the CVD method so as to cover the dielectric thin film (35).

Next, as shown in FIG. 1F, this time the oxide film (27) on the surface of the base region (31) of the NPN transistor and the surface of the island (25).
Is opened and phosphorus (P) is deposited by using this oxide film (27) as a mask to form an N ⁺ type emitter region (36) and a collector contact region (37). Then, the emitter region (36) is diffused to a desired depth by applying heat treatment in an oxidizing or non-oxidizing atmosphere (drive-in).
And, to control the h _FE of the NPN transistor.

Next, as shown in FIG. 1G, a resist pattern made of a negative or positive photoresist is formed on the oxide film (27),
Dielectric thin film by wet or dry etching (35)
The upper oxide film (27) is removed, and a contact hole for electrical connection is opened in a desired portion of the oxide film (27). Then, an aluminum layer is formed on the entire surface of the substrate (21) by a known vapor deposition or sputtering technique, and the aluminum layer is patterned again to form an electrode (38) having a desired shape and an upper electrode (39) on the dielectric thin film (35). ) Is formed.

According to the above-described manufacturing method of the present application, the lower electrode region of the MIS type capacitor is formed by utilizing the upper diffusion layer (26) forming process of upper and lower separation.
Since (28) is formed, the dielectric thin film (35) can be formed prior to emitter diffusion. Also, the formation of the resistance region (30) by ion implantation can be performed prior to the emitter diffusion. Therefore, phosphorus for forming the emitter region (36)
It is not necessary to place a heat treatment for incorporating an optional device between the deposit of (P) and the drive-in of phosphorus (P), and the _hFE control of the NPN transistor is immediately performed from the state where phosphorus (P) is initially diffused by the deposit. it is possible to shift to a heat treatment for, of the NPN transistor h _FE
Can be significantly suppressed. Also, since the heat treatment conditions for the emitter region (36) can be unified regardless of whether or not optional devices are incorporated, the process control for each model becomes extremely easy.

Further, according to the above-described embodiment, since the base electrode (31) and the resistance region (30) can be photoetched only once without using a single process for forming the lower electrode region (28),
The process can be simplified.

By the way, the lower electrode region (28) of the MIS type capacitor of the present application takes various embodiments. FIG. 2 shows a second embodiment of the present application, which is an example applied to an IC of a normal separation type rather than upper and lower separation. As is clear from the figure, the lower electrode region (28) of the MIS type capacitor is formed at the same time as the formation of the isolation region (40), and the entire bottom surface of the lower electrode region (28) is made to collide with the buried layer (22). Has a structure in which the lower electrode of the MIS type capacitor is separated from the ground potential of the substrate (21). Further, FIG. 3 shows the third of the present application.
And an example applied to an IC provided with an N ⁺ -type collector low resistance region (41) for the purpose of reducing V _CE (sat) of an NPN transistor. As is clear from the figure,
Simultaneously with the formation of the collector low resistance region (41), the lower electrode region (28) of the MIS type capacitor is formed. Since the second and third embodiments do not use a single process, they can be efficiently incorporated, but it goes without saying that a single process may be used if it is allowed.

(G) Effect of the Invention As described above, according to the present invention, there is provided a method of manufacturing a semiconductor integrated circuit capable of solving the difficulty of h _FE control of an NPN transistor due to incorporation of a MIS type capacitor and a resistance element by ion implantation. It has the advantage that it can. In addition, since the heat treatment conditions for the emitter region (36) can be unified, the process control for each model can be simplified, and there is also the advantage that it is possible to perform heat treatment on different types of wafers at the same time in a small number of different models. Have.

Further, according to the embodiment of the present application, since the base electrode 31 and the resistance region 36 can be commonly etched without requiring a single process for forming the lower electrode, there is an advantage that the manufacturing process can be extremely simplified.

[Brief description of drawings]

1A to 1G are sectional views for explaining the present invention,
2 and 3 are sectional views for explaining the second and third embodiments of the present invention, and FIG. 4 is a sectional view for explaining the conventional example. (21) is a P-type substrate, (28) is a lower electrode region of MIS-type capacitance, (30) is a resistance region, (31) is a base region of an NPN transistor, (35) is a dielectric thin film of MIS-type capacitance, ( 3
6) is the emitter region of the NPN transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 27/04 R 8427-4M (72) Inventor Chikao Fujinuma 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 18 in Sanyo Electric Co., Ltd. (56) Reference JP-A-57-73963 (JP, A) JP-A-61-99364 (JP, A)

Claims (1)

[Claims] 1. A step of forming a buried layer of opposite conductivity type in a desired region of a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of opposite conductivity type on the substrate, and a separation for separating the epitaxial layer. Forming the lower electrode region of the MIS-type capacitor at the same time as the formation of the region or at the same time as the formation of the collector low resistance region of the vertical bipolar transistor, the transistor is formed on the first island surface on the epitaxial layer. Forming a selection mask for forming a resistance element having a resistance portion on the second island and a contact portion at both ends of the resistance portion for forming a base region; Type ion implantation of impurities twice, one of the two ion implantations is a dose determining the specific resistance of the resistance portion. And the other has a dose amount such that the other is added to the one dose amount to determine the specific resistance of the base region of the transistor, and the entire surface of the base region of the transistor and the contact portion of the resistance element are Both the one and the other ion implantations are performed, and the resistance portion is subjected to only the one ion implantation using a selection mask; and an opening partially exposing the insulating film on the surface of the lower electrode region. Forming a portion and forming a dielectric thin film of the MIS type capacitor made of a silicon nitride film by a CVD method so as to cover the opening, by selectively diffusing impurities of opposite conductivity type on the surface of the base region. Forming an emitter region of the bipolar transistor, covering the entire surface with an electrode material, and patterning the same to form an upper electrode for covering the dielectric thin film and each diffusion The method of manufacturing a semiconductor integrated circuit, characterized by comprising the step of forming an electrode to contact the band.