JPH0626307B2 - Pulse generator - Google Patents

Description

The present invention relates to an improvement of a pulse generation circuit that outputs a serial pulse signal having a predetermined number of pulses.

[Prior Art] As a conventional pulse generation circuit, when the number of pulses to be output in one cycle is set by a microprocessor,
Some have output a serial pulse signal at a constant frequency.

However, in this pulse generation circuit, since the frequency of the output pulse signal is constant, the output signal becomes a burst pulse signal as shown in FIG. Therefore, if the receiving side of the output pulse is, for example, a drive circuit of the pulse motor, there arises a problem that the rotation of the pulse motor is not smooth.

As a pulse generation circuit that solves such a problem, there is one described in the application specification of Japanese Patent Application No. 62-168099 by the present applicant.

This pulse generation circuit reads data that gives an optimum output pulse period from a memory according to the number of pulses generated in one period, and outputs this data to a DDA (Digital D
It is set in an differential adder circuit and a smooth pulse signal is generated by a carry signal of the DDA circuit.

[Problems to be Solved by the Invention] However, in this pulse generation circuit, the microprocessor is configured to generate a serial pulse at a timing at which the number of output pulses of one cycle is set. Therefore, as shown in FIG. 5, when the setting timing is shifted due to the interrupt processing of the microprocessor or the like, the output pulse number of the next cycle is set before the set number of pulses are output. It may end up. In order to prevent this, the software of the microprocessor must be software in which the variation in setting timing is minimized. For this reason, there is a problem that the load on the software increases.

The present invention has been made to solve such a problem, and it is an object of the present invention to realize a pulse generation circuit capable of generating a set number of smooth pulses without being affected by a timing shift defined by software. To aim.

[Means for Solving Problems] In the present invention, the number of pulses generated in one cycle is set, the count is changed when the pulse is input, and a count-up signal is output when the count is changed by the set value. A counter, a memory in which data that gives an optimum output pulse period corresponding to the set value of the counter is stored, and when activated by a trigger signal given by hardware,
Start-up means for enabling the memory, reading data giving an optimum output pulse period from the memory using the set value of the counter as an address signal, and generating a latch signal for latching the read data; A DDA circuit that latches the data read from the memory when a latch signal is generated and outputs a carry signal in a cycle according to the data; and a carry signal of the carry signal when the counter generates a count-up signal. A pulse generation circuit comprising: a pulse inhibition circuit that inhibits passage and terminates output of a serial pulse signal.

[Examples] The present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram of an embodiment of a pulse generating circuit according to the present invention.

In FIG. 1, reference numeral 1 is a latch for holding and outputting data of the number of pulses generated in one cycle. The data held in the latch 1 is 16-bit data, and this data is time-divided by the 8-bit data buses D0 to D7.

Reference numeral 2 denotes a counter, for example, a down counter, which counts down each time the data output from the latch 1 is set and a pulse signal is input, and generates a count-up signal CU when the count reaches 0. This counter is 1
This is a 4-bit counter, and the set value is given by 16-bit data buses ID0 to ID15.

3 is a logic circuit, which is PLOADL, PLOAD
H, SYNC / ASYNC, TRRIGER signals are given.

The PLOADL and PLOADH signals are signals used for time-divisionally latching the lower byte and the upper byte of the 16-bit data held in the latch 1. These signals are given to the latch 1 through the NAND gates 31 and 32, and the OR gates 33 and 34 and the AND gate 3 are provided.
It is also given to the down counter 2 via 5, 36.

The SYNC / ASYNC signal is a switching signal for synchronous / asynchronous operation. This signal is given to the NAND gates 31, 32, the OR gates 33, 34, and the AND gate 37.
The synchronous and asynchronous operations will be described later.

The TRRIGER signal is a signal that triggers the setting of the number of output pulses. This signal is given to the AND gate 37.

Reference numeral 4 denotes a mono-multivibrator, which operates with a CLOCK signal, receives the output of the AND gate 37, and supplies the output to the AND gates 35 and 36.

Reference numeral 5 denotes a memory, and data for giving an optimum output pulse cycle corresponding to the set value is stored in an address determined by the set value of the down counter 2. This memory 5
For this, an external ROM or the like is used.

A sequencer 6 operates at a timing given by the CLOCK signal and is activated by the TRRIGER signal based on the level of the output signal of the AND gate 36. When the sequencer 6 is activated, the enable signal ROMOE
Enable the memory 5 by DLATCH, UL
The ATCH signal is generated and the GATE signal is generated. When the memory 5 is enabled, the address buses RA1 to RA
A 14-bit address determined by 14 as a set value is sent to the memory 5.

Reference numeral 7 is a first flip-flop, 8 is a full adder, and 9 is a third flip-flop, which form a DDA circuit.

The first flip-flop 7 latches and outputs the data read from the memory 5.

The read data is 16-bit data, and the read data is transmitted by 8-bit data buses RD0 to RD7. Therefore, reading and latching must be performed in a time division manner. The time division of reading is performed by a signal transmitted from the sequencer 6 through the 1-bit address bus RA0.

The time division of the latch is performed by DLATCH and ULATCH.

The full adder 8 receives the output of the first flip-flop 7 and gives the added value to the second flip-flop 9.

The second flip-flop 9 is provided with an addition value of the full adder 8 and an ADDER CLOC from a pulse inhibition circuit described later.
K is entered. The second flip-flop 9 latches the added value of the full adder 8 at the timing of ADDER CLOCK and feeds this value back to the input section of the full adder 8.

The full adder 8 adds the outputs of the first flip-flop 7 and the second flip-flop 9, and gives the added value to the second flip-flop 9. The second flip-flop 9 generates a carry pulse signal F each time the most significant bit of the latched data changes. Carry signal F is DD
It becomes the output of the A circuit.

The first flip-flop 7, the full adder 8 and the second flip-flop 9 handle 16-bit data.

Reference numeral 10 denotes a pulse prohibiting circuit, which outputs the carry signal F to the outside and gives it to the down counter 2 before the down counter 2 generates the count up CU signal, and when the count up signal occurs, the pulse prohibiting circuit 10 enters the prohibit state. Therefore, the passage of the carry signal F is prohibited. The carry signal output to the outside becomes the output signal of the pulse generating circuit. Further, the pulse prohibition circuit 10 is CL when it is not in the prohibition state.
It passes through the OCK signal and is given to the second flip-flop 9 as ADDER CLOCK. When it is in the prohibited state, the passage of the CLOCK signal is prohibited.

An error detection circuit 11 is provided with a signal S from the AND gate 35 and the pulse prohibition circuit 10 indicating whether or not it is in a prohibition state. Based on these signals, the down counter 2 is provided to the down counter 2 during generation. When a new number of output pulses is set, an error signal ERROR is generated. Signal S
Is a handshake signal that informs the microprocessor whether or not the pulse generation circuit is in a state where the number of output pulses can be set.

Here, the activation means in the claims corresponds to the logic circuit 3, the mono-multivibrator 4, and the sequencer 6.

The transmission signals of PLODL, PLOADH, CLOCK and the data bus are given from the microprocessor.

Next, the operation of such a circuit will be described.

FIG. 2 is a time chart of each signal when the SYNC / ASYNC signal is at low level. In this case, the output pulse number setting timing is given by the software executed by the microprocessor. Further, the AND gate 37 is closed and the passage of the TRRIGER signal is prohibited.

PLOADH, PLODL, ULATCH, DLAT
The CH signal is read at the timing of rising from the low level to the high level, and the ROMOE signal enables the memory 5 when it goes to the low level.

The number of pulses generated in one cycle is set in the down counter 2 by the PLOADH signal and the PLOADL signal from the microprocessor.

After setting the number of pulses, the sequencer 6 starts to move,
Using the set value of the down counter 2 as an address, data that gives an optimum output pulse period corresponding to the set value is read from the memory 5 and set in the first flip-flop 7. When the setting is completed, the pulse prohibition circuit 10 becomes AD
Apply DER CLOCK to the second flip-flop 9. As a result, the full adder 8 starts moving.

The second flip-flop 9 latches the output of the full adder 8, that is, the added value of the first flip-flop 7 and the second flip-flop 9 in a cycle of ADDER CLOCK. The second flip-flop 9 generates a carry signal F (pulse signal) each time the most significant bit of the latched output changes. The number of pulses of the carry signal F is counted by the down counter 2.

When the down counter 1 generates the count-up signal CU, the pulse inhibition circuit 10 inhibits the passage of the CLOCK signal and does not give it to the second flip-flop 9. As a result, the second flip-flop 9 does not generate the carry signal, and the generation of the serial pulse signal ends.

When the error detection circuit 11 sets a new number of output pulses in the down counter 2 during generation of a serial pulse, an error signal ERROR is generated.

Next, a case where the SYNC / ASYNC signal becomes high level will be described. The time chart in this case is as shown in FIG.

The difference in operation between when the SYNC / ASYNC signal is at low level will be described.

Gate 37 passes the TRRIGER signal. TRRI
When the GER signal becomes high level, the sequencer 6 starts to operate, the ROMOE signal and the DLATCH and ULATCH signals are made low level, and the data giving the optimum output pulse period is read from the memory 5 and set in the flip-flop 7.

The TRRIGER signal is provided separately from the operation of the microprocessor.

The subsequent operation is the same as when the SYNC / ASYNC signal becomes low level.

[Effect] According to the present invention, it is possible to prevent the read data from the memory from being set in the DDA circuit only after the activation by the TRRIGER signal. Therefore, even if the output pulse number setting timing specified by software is deviated, All the set number of pulses can be generated in a cycle. As a result, a smooth number of pulses can be output without being affected by the timing deviation specified by software.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a pulse generating circuit according to the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the circuit of FIG. 1, and FIGS. 6 is a time chart for explaining the operation of the pulse generation circuit. 2 ... Down counter, 3 ... Logic circuit, 4 ... Mono multivibrator, 5 ... Memory, 6 ... Sequencer, 7 ... First flip-flop, 8 ... Adder,
9 ... Second flip-flop, 10 ... Pulse inhibition circuit.

Claims (1)

[Claims] 1. A counter that outputs a count-up signal when the number of pulses generated in one cycle is set, the count changes when the pulse is input, and the count changes by the set value, and the set value of the counter When activated by a memory that stores data that gives the corresponding optimum output pulse period and a trigger signal that is given by hardware,
Start-up means for enabling the memory, reading data giving an optimum output pulse period from the memory using the set value of the counter as an address signal, and generating a latch signal for latching the read data; A DDA circuit that latches the data read from the memory when a latch signal is generated and outputs a carry signal in a cycle according to the data; and a carry signal of the carry signal when the counter generates a count-up signal. A pulse generation circuit comprising: a pulse inhibition circuit that inhibits passage and terminates output of a serial pulse signal.