JPH0636489B2 - Pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an improvement of a pulse generation circuit for generating serial pulses of a predetermined number of pulses.

[Prior Art] As a pulse generator for setting the number of output pulses by a microprocessor (hereinafter referred to as μP), there is one described in the application specification of Japanese Patent Application No. 62-168099 by the present applicant. This pulse generation circuit changes the pulse frequency according to the number of output pulses to generate smooth pulses at equal intervals.

[Problems to be Solved by the Invention] However, in this pulse generation circuit, it is necessary to keep the timing of setting the number of output pulses constant, and if this timing is delayed, the smoothness of the pulses is impaired as shown in FIG. There was a problem.

The present invention has been made in order to solve such a problem, and has a degree of freedom in the setting timing of the output pulse number from the μP, and the delay of the setting timing does not affect the output pulse number. The purpose is to realize.

[Means for Solving the Problem] According to the present invention, a preset buffer for presetting the data of the output pulse number is provided, and the data of the output pulse number of the next cycle is set in this preset buffer during this cycle. It is characterized by.

[Examples] The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a pulse generating circuit according to the present invention.

In the figure, 1 is a preset buffer in which data of the number of output pulses in one cycle is preset. The preset value is μ
8-bit data bus IDB0-7 from P (not shown)
Given via. Since the number of bits of the preset value is larger than the number of bits of the data bus, the upper byte load signal ▲ ▼ and the lower byte load signal ▲ ▼
Use ▼ properly and set in time division. The number of output pulses of the next cycle is preset in this buffer during the current cycle.

A down counter 2 is set with a preset value of the preset buffer 1 and counts down each time a pulse is output, and outputs a count-up signal when the count reaches 0. After the count-up signal is generated, the data of the next output pulse number is set from the preset buffer 1.

A latch 3 takes out the most significant bit of the output pulse number data and holds and outputs the signal SIGN indicating the pulse direction. When driving the motor with output pulses, SI
The GN signal is a signal that determines the rotation direction of the motor.

Reference numeral 4 denotes a memory, which stores the optimum pulse frequency corresponding to the set value with the set value of the down counter 2 as an address. A ROM is used as the memory 4, and an address to the memory 4 is a 15-bit address bus RA0.
~ 14.

A status buffer 5 reads the status signal ▲ ▼ from the preset buffer 1 by the status read signal ▲ ▼.

6 is a control logic, which is a clock signal CLO
It operates at the timing given by CK, and stores the set value from the preset buffer 1 to the down counter 2 and controls the reading of data from the memory 4.

Reference numeral 7 is a rate latch, 8 is a full adder, and 9 is a latch. With these, DDA (Digital Differential)
ial Adder).

The rate latch 7 latches and outputs the data read from the memory 4. Read data is transferred by the 8-bit data buses RD0 to RD7.

Since the number of bits of data read from the memory 4 is larger than 8 bits, the upper bit and the lower bit are read separately according to the state of the least significant bit of the read address given to the memory 4. This least significant bit is transferred by the address bus RA0.

Further, since the number of bits of data latched in the rate latch 7 is larger than 8 bits, this data is latched in time division using the lower byte load signal ▲ ▼ and the upper byte load signal ▲ ▼. ▲
The control logic 6 generates ▼ and ▲ ▼.

The full adder 8 adds the outputs of the rate latch 7 and the latch 9 and gives the added value to the latch 9.

To the latch 9, the added value of the full adder 8 and the clock CLK1 from the control logic 6 are given. The latch 9 latches the added value of the full adder 8 at the timing of the clock CLK1 and feeds back the added value to the input section of the full adder 8.

The full adder 8 adds the outputs of the rate latch 7 and the latch 9 and gives the added value to the latch 9. The carry signal ADDCY (pulse signal) is generated at the output of the latch 9 every time the most significant bit changes. The carry signal ADDCY becomes the output of the DDA circuit.

The frequency of the clock CLK1 is set higher than the frequency at which data is latched in the rate latch 7.

Reference numeral 10 is an AND gate, which allows the carry signal to pass before the down counter generates the count up signal by the signal GC from the control logic 6 and prohibits the carry signal from passing when the count up signal occurs. The signal that has passed through the AND gate 10 becomes the output pulse of the pulse generation circuit.

▲ ▼ is an initial reset signal given to the preset buffer 1, the down counter 2, the latches 3, 9, the control logic 6, and the rate latch 7.

▲ ▼, ▲ ▼, ▲
The signals ▼ and ▲ ▼ are given from μP.

Next, the operation of such a pulse generating circuit will be described.

FIG. 2 is a time chart of each signal of the circuit of FIG.

First, the data of the number of pulses generated during one cycle is set in the preset buffer 1 by the signal and the signal from the μP.

At this time, the content of the most significant bit of the set value is set in the latch 3, and the signal SIG indicating the pulse direction is thereby set.
N is output.

When the data setting by ▲ ▼ is completed, the buffer write signal ▲ ▼ becomes high level,
As a result, the control logic 6 becomes the clock CLOC.
The operation is started at the timing of K, and the data of the output pulse number is loaded into the down counter 2 by the CLOAD signal.

Next, using the set value in the down counter 2 as an address, the initial value of the full adder 8, that is, the data of the optimum output pulse frequency is read from the memory 4 and set in the rate latch 7.

When the setting is completed, the control logic 6 gives the clock CLK1 to the latch 9. With this, the full adder 8
Begins to move.

The latch 9 is the output of the full adder 8, that is, the rate latch 7
And the added value of the output of the latch 9 is latched and output at the cycle of the clock CLK1. The carry signal ADDCY is generated each time the most significant bit of the output of the latch 9 changes. ADDC
The Y signal is counted by the down counter 2.

As soon as the full adder 8 starts moving, the signal ▼ becomes low level, and the data of the output pulse number of the next cycle can be written in the preset buffer 1. The data writing of the output pulse number of the next cycle is performed until the pulse output of the current cycle is completed.

When the pulse number of the next cycle is written in the preset buffer 1, the signal ▲ ▼ returns to the high level.

When the count of the down counter 2 becomes 0 and a count-up signal is generated, the control logic 6 closes the gate 10 and ends the output of the pulse of this cycle. At this time, when the data of the output pulse number is written in the preset buffer 1, that is, when the signal ▼ is at the high level, the operation after the above-mentioned loading of the data of the output pulse number to the down counter 2 is performed. .

FIG. 3 is a block diagram of another embodiment of the pulse generating circuit according to the present invention.

In this circuit, in addition to the preset buffer for setting the output pulse number data, a preset buffer 1 ₁ for setting the output pulse frequency data is provided, and the output pulse number and the output pulse frequency are set to buffers 1 and 1 ₁ by μP. It is something to set. In this circuit, data for giving an optimum output pulse frequency corresponding to the preset value of the preset buffer 1 ₁ is stored in the memory 4 ₁ .

Then, when the frequency data of the output pulse is preset in the preset buffer 1 ₁ , the control logic 6 reads the data of the optimum output pulse frequency from the memory 4 ₁ using the preset value as an address.

Further, after the DDA circuit latches the data, the preset buffer 1 ₁ frequency data of the output pulse of the next cycle during this period is preset.

Note that an up counter may be used instead of the down counter down counter 2.

Further, in the embodiment, the case where the preset buffer has one stage has been described, but the FIFO (First In First Out Memory)
For example, the preset buffer may have two or more stages. By doing so, the degree of freedom of the pulse number setting period of μP is increased and it becomes easier to use.

Further, the number of bits of the transfer signal of each bus may be other than that shown in the embodiment.

[Effect] According to the present invention, since the preset buffer that can set the next output pulse number during the current cycle is provided,
The number of output pulses can be set ahead of time, and the flexibility of setting timing of the μP software can be increased.

Further, since the delay in the output pulse number setting timing is reduced, the output suspension period between each pulse output cycle can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a pulse generation circuit according to the present invention, FIG. 2 is an operation explanatory view of the circuit of FIG. 1, and FIG. 3 is a diagram of another embodiment of the pulse generation circuit according to the present invention. The configuration diagram and FIG. 4 are time charts of pulses output from a conventional pulse generation circuit. 1 ... Preset buffer, 2 ... Down counter, 4
... Memory, 6 ... Control logic, 7 ... Rate latch, 8 ... Full adder, 9 ... Latch, 10 ... Gate.

Claims (2)

[Claims] 1. A preset buffer in which the data of the output pulse number of one cycle is preset, and when the DDA circuit described later latches the data, the data of the output pulse number of the next cycle is preset during the current cycle, The preset value of this preset buffer is set,
The counter fluctuates each time a pulse is output, and a counter that generates a count-up signal when it fluctuates by the set value, a memory that stores data that gives the optimum output pulse frequency corresponding to the set value of this counter, When a preset value is set in the counter, a controller that reads the data of the optimum output pulse frequency from the memory using the set value as an address, and the data read by the controller is latched and output at a cycle according to this data. A pulse generator characterized by comprising: a DDA circuit for generating a carry signal which becomes a pulse; and a gate for inhibiting passage of the carry signal and ending the generation of an output pulse when the count-up signal is generated. circuit. 2. A first preset buffer in which the data of the output pulse number of one cycle is preset, and the data of the output pulse number of the next cycle is preset during the current cycle when the DDA circuit described later latches the data. A second preset buffer in which the frequency data of the output pulse is preset, and the frequency data of the output pulse of the next cycle is preset during the current cycle after the DDA circuit described later latches the data. Corresponding to the preset value of the second preset buffer, and the counter that generates the count-up signal when the preset value of the preset buffer is set, the count changes each time a pulse is output, and the count changes by the set value Memory that stores data that gives the optimum output pulse frequency When a preset value is set in the counter, a controller that reads the optimum frequency data of the output pulse from the memory by using the preset value of the second preset buffer as an address, and latches the data read by the controller. A DDA circuit for generating a carry signal which becomes an output pulse at a cycle corresponding to the data, and a gate for inhibiting passage of the carry signal and ending the generation of the output pulse when the count-up signal is generated. A pulse generation circuit characterized by being provided.