JPH0626450B2 - Static overcurrent detector - Google Patents

Description

The present invention relates to a current detection method for a static overcurrent detection device that detects a fault current.

[Prior Art] FIG. 6 shows a control circuit of a conventional static overcurrent detection device as disclosed in, for example, JP-A-60-32512. In the figure, current detecting current transformers (21), (22) and (23) are provided for each phase of a plurality of phases (three phases of R, S and T in this example) of the electric circuit. Full-wave rectifier circuits (31), (32), (33) on the secondary side of each current transformer (21), (22), (23) to obtain the absolute value of the secondary output.
Are connected respectively. Each full-wave rectifier circuit (31), (32),
Burden circuits (41), (42), and (43) are connected to the output side of (33), respectively. The first output terminals of the burden circuits (41), (42) and (43) are connected to the corresponding signal conversion circuits (91), (92) and (93), respectively. This is for obtaining the effective value or the average value of the output signals induced in the respective burden circuits (41), (42), (43) of the signal conversion circuits (91), (92), (93). Signal conversion circuit (91), (9
2) and (93) output signals correspond to the corresponding diodes (161), (16
2) and (163) are input to the OR circuit (160). The second output terminals of the burden circuits (41), (42), (43) are the respective inputs of the OR circuit (130) as the maximum value detecting means, which are diodes (131), (132), (133), respectively. It is connected to the terminal. OR
The circuit (130) outputs a signal corresponding to the maximum value of the current flowing through the AC electric circuit (10). The output side of the OR circuit (130) is connected to the time generation circuit (150) via the Zener diode (140). Output terminal of time generation circuit (150) is thyristor
It is connected to the gate of (120). In addition, the signal conversion circuit (9
OR circuit for the maximum output signal among 1), (92) and (93)
A / D to receive via (160) and convert to digital signal
A conversion circuit (100) is provided. A / D conversion circuit (100)
Each output of is input to the microcomputer (110).
The A / D conversion circuit (100) and the microcomputer (110) are provided with a power supply circuit (500) as an operating power supply.
The output signal of the microcomputer (110) is input to the thyristor (120). Output device (80) having output terminal (81) in series with thyristor (120)
Are connected.

When a fault current flows through the AC circuit (10) in the static overcurrent detection device configured as above, the current transformers corresponding to each phase
(21), (22), and (23) detect the above-mentioned fault current with a current ratio unique to them and induce an output current on the secondary side. Each output current is converted into direct current by full-wave rectifier circuits (31), (32), (33),
It is supplied to the corresponding burden circuits (41), (42), (43), respectively. The output signals of the load circuits (41), (42), (43) are converted into signals corresponding to their effective or average values by the signal conversion circuits (91), (92), (93) for each phase. To be done. Signal conversion circuit
The effective value or average value output of (91), (92), (93) is the OR circuit (1
These maximum values are input to the A / D conversion circuit (100) via 60). The A / D conversion circuit (100) converts the analog signal thus input into a digital signal. This digital signal is input to the microcomputer (110),
The microcomputer (110) determines the level of this digital signal input according to a predetermined program. Further, a predetermined timed operation is performed based on the result of the level discrimination, and an output signal is output from the output port (116). The output signal emitted from the output port (116) of the microcomputer (110) is applied to the gate of the thyristor (120). The thyristor (120) is triggered by this signal to turn on and drive the output device (80). And the output device (8
An output signal is obtained from the output terminal (81) of 0).

On the other hand, the voltage signal corresponding to the fault current induced in the burden circuits (41), (42) and (43) is input to the OR circuit (130) including the diodes (131), (132) and (133). It The output side of the OR circuit (130) is a time generation circuit via the Zener diode (140).
Since it is connected to (150), when the output level of the OR circuit (130) exceeds the zener voltage of the zener diode (140), a signal is input to the time generation circuit (150). The time limit generation circuit (150) performs a predetermined time delay operation based on this signal, and triggers the gate of the thyristor (120). The thyristor (120) is triggered and turned on as described above, and an output signal is obtained from the output terminal (81) of the output device (80).

[Problems to be Solved by the Invention] Since the conventional static overcurrent detection device is configured as described above, firstly, the effective value (or average value) of the fault current of each phase is detected, and The maximum value (OR circuit output value) must be obtained. Secondly, if the input signal of each phase fluctuates and the maximum phase discrimination is frequently switched, there is a problem that the phase difference of the input signal and other effective value conversion (or average value conversion) cannot be accurately detected. The circuit is complicated and expensive, and a step of adjusting the output level of each detection circuit is required.

The present invention has been made to solve the above problems, and provides an inexpensive and highly reliable static overcurrent detection device in which the output level adjustment of the detection circuit is eliminated with a simple circuit configuration. It is an object.

[Means for Solving Problems] The static overcurrent detection device according to the present invention uses a maximum phase discrimination circuit to detect a fault current, and the operation of the maximum phase discrimination circuit has a hysteresis characteristic. Characterize.

[Operation] The maximum phase discrimination circuit discriminates the maximum one of the fault currents of each phase by increasing the threshold value according to the hysteresis characteristic, improves the reliability of the maximum phase discrimination, and only the reliable signal is the effective value. The fault current is detected by guiding it to the (or average value) detection circuit.

[Embodiment] FIG. 1 shows an embodiment of a static overcurrent detection device according to the present invention. In FIG. 1, the components with the same numbers as in the conventional example shown in FIG. 6 have the same functions.

Current transformers (21), (2
2) and (23) are provided respectively. Each current transformer (21), (2
Full-wave rectifier circuits (31), (32), and (33) for obtaining the absolute value of the secondary output are connected to the secondary sides of 2) and (23), respectively.
A burden circuit (4) is provided on the output side of each full-wave rectifier circuit (31), (32), (33).
1), (42) and (43) are connected respectively. Each burden circuit (4
Each of the first output terminals (1), (42), and (43) (the output terminal of the signal whose level is finely adjusted) is configured to output only the signal of the largest signal source among the input signals. It is connected to the maximum phase discrimination circuit (400) having a hysteresis characteristic.
The output terminal that outputs the signal discriminated by the maximum phase discrimination circuit (400) is connected to the signal conversion circuit (90). The signal conversion circuit (90) is for obtaining an effective value or an average value of the signals discriminated by the maximum phase discrimination circuit (400). The second output terminals of the burden circuits (41), (42) and (43) are respectively maximum in order to obtain the second output signal of the current sensor means composed of the diodes (131), (132) and (133). O as a value detection means
It is connected to each input terminal of the R circuit (130). The ends of the respective burden circuits (41), (42), (43) on the side opposite to the second output terminal are connected to a common potential point (earth). Where the current transformers (21), (22), (23), full-wave rectifier circuits (31), (32), (3
3) The burden circuits (41), (42), (43) constitute a current detection circuit (200) for detecting the current of the AC electric circuit (10). OR circuit (130)
Outputs a signal corresponding to the maximum value of the current flowing through the AC circuit (10). The output side of the OR circuit (130) is connected to the time generation circuit (150) via the Zener diode (140).
The output terminal of the time generation circuit (150) is connected to the gate of the thyristor (120). Further, an A / D conversion circuit (100) for converting the output signal of the signal conversion circuit (90) into a digital signal is provided. Each output of the A / D conversion circuit (100) is input to the microcomputer (110). A / D conversion circuit (100)
A power supply circuit (500) is provided as a power supply for operating the microcomputer (110). The output signal of the microcomputer (110) is input to the thyristor (120). An output device (80) having an output terminal (81) is connected in series to the thyristor (120).

Fig. 2 shows the maximum phase discrimination circuit (40
A specific circuit configuration of (0) is shown. Input terminals (401), (402), (4
03) receives the signals given from the burden circuits (43), (44), (45) of each phase and inputs them to operational amplifiers (hereinafter abbreviated as OP amplifiers) (OP1), (OP2), (OP3). To do. Each OP amplifier is configured as a unity gain amplifier, and the output terminal of each OP amplifier is a resistor (R
1), (R2). It is connected to one terminal of (R3) and each input terminal of analog switches (AS1), (AS2), and (AS3). Resistance (R1), (R2), (R
The other ends of 3) are capacitors (C1), (C2),
One end of (C3) and OP amplifiers (OP4), (OP
5) and (OP6) are connected to the positive input terminals. Each O
The output terminals of the P amplifiers (OP4), (OP5), (OP6) are connected to the diodes (D1), (D2), (D3) and the anode side, and the diodes (D1), (D2), (D) are connected.
The cathode side of 3) is commonly connected as the same potential, and is connected to the negative input terminals of the OP amplifiers (OP4), (OP5), and (OP6) through resistors (R16), (R17), and (R18), respectively. And constitutes a maximum phase detection circuit. The output terminals of the OP amplifiers (OP4), (OP5), (OP6) are zener diodes (ZD1),
Zener diodes (ZD1), (ZD2), (ZD3) connected to the anode side of (ZD2), (ZD3).
On the cathode side of the transistors through the resistors (R4), (R5), (R6), transistors (TR1), (TR2), (TR3)
Connected to the base of. Transistor (TR1),
Each of (TR2) and (TR3) is a PNP type transistor, and its collector is connected to a negative power source (-Vcc). The resistors (R10), (R11) and (R12) are connected between the base and the collector in order to apply a bias voltage to each of the transistors (TR1), (TR2) and (TR3). Resistance (R7), (R
8) and (R9) each have a transistor (TR) at one end.
1), (TR2), and (TR3), and the other end is connected to a positive power source (Vcc). The emitters of the transistors (TR1), (TR2), (TR3) are analog switches (AS1), (AS2), (AS).
It is connected to the gate of 3). The output terminals of the analog switches (AS1), (AS2) and (AS3) are both connected to the output terminal (404) of the maximum phase discrimination circuit. Transistors (TR1), (TR2), (TR
Each emitter of 3) is an analog switch (AS4), (A
The gates of S5) and (AS6) are respectively connected. In addition, analog switches (AS4), (AS5),
One end of the input terminal of (AS6) is grounded, and the other end is negative input of each of OP amplifiers (OP4), (OP5) and (OP6) via resistors (R13), (R14) and (R15). It is connected to the terminal. In addition, positive power supply (Vcc),
Negative power supply (-Vcc) and ground (GND) are OP amplifiers (OP1) to (OP6) and analog switch (AS).
It is connected as a power supply necessary for operating each of the elements 1) to (AS3).

The configuration and processing steps of the microcomputer (110) will be described with reference to the block diagram shown in FIG. 3 and the flowchart shown in FIG. In FIG. 3, the microcomputer (110) includes a data bus (112) and an address bus (11
3) via CPU (111), ROM (114), RAM (115)
And an I / O port (116). A part of the data bus (112) and the address bus (113) are connected to the A / D conversion circuit (100). Generally, the ROM (114) includes a program for executing predetermined signal processing, and the CPU
(111) executes the program in synchronization with a predetermined clock signal. The RAM (115) functions as a register necessary for signal processing. In the flowchart shown in FIG. 4, at least a first level discriminating means (step 3) of the input signal as a basic function, and a first time period generating means (for executing a predetermined time delay operation according to the level discriminated value ( Step 5) is included. The flow chart also includes reset means (step 9) configured to execute the reset operation with time at a reduction rate along a predetermined heat radiation characteristic (heat radiation characteristic of the electric circuit and the load). This reset means (step 9) is the first time generation means (step 5) or the time generation means (1) shown in FIG.
50) It operates when the input signal to at least one of the (second time period generating means) becomes lower than a predetermined level.

Since the static overcurrent detection device according to the present invention is configured as described above, when a fault current flows in the AC circuit, the current transformers (21), (22), (23) corresponding to the respective phases are The fault current is detected by the rectification ratio peculiar to them, and the output current is induced on the secondary side. Each output current is full-wave rectifier circuit (31), (32), (33)
Are converted to DC by each corresponding burden circuit (41), (42), (43)
Is supplied to each. At this time, the burden circuit (41), (42), (4
The signal voltage waveform induced in 3) is a known absolute value waveform.
The output signal of each burden circuit (41), (42), (43) is the maximum value discriminating circuit (4) that discriminates and outputs only the signal of the maximum phase among the signals of each phase.
00) and is input to the signal conversion circuit (90) and converted into signals corresponding to the effective value or average value of those signals. The effective value or average value output of the signal conversion circuit (90) is input to the A / D conversion circuit (100). The A / D conversion circuit (100) converts the analog signal thus input into a digital signal. This digital signal is a microcomputer (110)
Then, the microcomputer (110) determines the level of the digital signal input according to a predetermined program. Further, a predetermined time-delaying operation is performed based on the result of the level discrimination, and an output signal is emitted from the output port (116). Microcomputer (110) output port (116)
The output signal emitted by the thyristor is applied to the gate of the thyristor (120). The thyristor (120) is triggered by this signal to turn on and drive the output device (80)
The output signal for fault current occurrence display or line protection or monitoring can be obtained from (81). On the other hand, burden circuits (41), (42),
The voltage signal corresponding to the induced fault current (43) is input to the OR circuit (130) including the diodes (131), (132) and (133). The output side of the OR circuit (130) is a Zener diode
Since it is connected to the time generation circuit (150) via (140), the output level of the OR circuit (130) is a zener diode.
When the Zener voltage of (140) is exceeded, a signal is input to the time generation circuit (150). The time limit generation circuit (150) performs a predetermined time delay operation based on this signal, triggers the gate of the thyristor (120) to drive the output device (80), and similarly the output terminal
The output signal is obtained from (81).

The full-wave signal obtained by the burden circuits (43), (44), (45) shown in FIG. 1 is the input terminal (401) of the maximum phase discrimination circuit (400) having the hysteresis characteristic shown in FIG. When input to (402) and (403), the respective input signals are OP amplifiers (OP1), (OP2), which form a unity-gain amplifier,
Through (OP3), analog switches (AS1), (A
S2), (AS3) input terminal and resistor (R1),
It is output to one terminal of (R2) and (R3). Resistors (R1), (R2), (R3) and capacitor (C
1), (C2), and (C3) respectively constitute an average value circuit for obtaining the average value of the input signal, and the obtained average value signal passes through resistors (R19), (R20), (R21). Input to the positive input terminals of the OP amplifiers (OP4), (OP5), and (OP6), respectively. OP amplifier (OP4), (OP
5), (OP6) and diodes (D1), (D
2) and (D3) constitute a maximum phase detection circuit that determines the maximum phase of each phase average value input, and includes diodes (D1) and (D3).
2), the average value output of the maximum phase is generated at the common cathode of (D3), and the OP amplifiers (OP4), (OP5), (OP6) are respectively passed through the resistors (R16), (R17), (R18).
Is fed back to the negative input terminal of. OP amplifiers other than the maximum signal of the average value input act as comparators,
Since the input signal is lower than the above-mentioned feedback potential, the OP amplifier is not inverted and the output maintains a voltage near the negative voltage (-Vcc). For example, assume that the maximum signal is input to the S phase in FIG. 2, that is, the terminal (402). The OP amplifier (OP5) acts as a normal positive-phase amplifier, and the average value as a threshold value is input to the negative input terminals of the other (R-phase and T-phase) OP amplifiers (OP4) and (OP6) via the diode (D2). Input the output. OP amplifier (OP4),
Since the positive terminal input of (OP6) does not reach this threshold value, each of the OP amplifiers (OP4) and (OP6) acts as a comparator, and each output has a negative voltage (-V).
cc) is maintained and the diodes (D1), (D
3) maintains the reverse bias state. Therefore, the Zener diodes (ZD1) and (ZD3) are reverse-biased, and the base currents sufficient to cause the transistors (TR1) and (TR3) to perform a switching operation are supplied (TR1) and (TR).
3) is conducted. Zener diode (ZD1),
The Zener voltages of (ZD2) and (ZD3) are the power supply voltage (V
A value slightly lower than cc) is selected and the transistor (TR
The emitter levels of 1), (TR2), and (TR3) are set to be equal to or lower than the ground potential (GND). When the transistors (TR1) and (TR3) are turned on, a signal that can sufficiently cut off the gate potentials of the analog switches (AS1) and (AS3) is applied to the positive input, so that the analog switches (AS1) and (AS3) are The cut-off state is set. On the other hand, since the output of the OP amplifier (OP5) to which the maximum phase is input is a positive voltage output according to the input signal, the Zener diode (ZD2) is in the cutoff state, and the base current of the transistor (TR2) is Not supplied, but a positive voltage is applied to the gate of the analog switch (AS2) through the resistor (R8). Therefore, only the analog switch (AS2) corresponding to the maximum phase input maintains the conductive state and outputs the output signal to the output terminal (404). At this time, as described above, the transistor (TR1),
Since the emitters of (TR2) and (TR3) are connected to the gates of analog switches (AS4), (AS5) and (AS6) respectively, the analog switch (AS
A signal of S phase, which is the maximum signal, is applied to the gate of 5), the analog switch (AS5) becomes conductive, and the potential of the negative input terminal of the OP amplifier (OP5) is lowered via the resistor (R14). That is, the OP amplifier (OP5) constitutes an amplifier with a positive phase input, and the OP amplifier (OP5)
The output voltage Vop of 5) is Given by. Here, Vsin is the average value input voltage of the S phase. That is, only the maximum phase input signal is
As shown in equation (1) Therefore, the hysteresis characteristic is apparently obtained. Therefore, by selecting and setting the respective resistance values of the resistors (R17) and (R14) in the equation (1), the threshold hysteresis voltage for maximum phase discrimination can be arbitrarily set. The same applies to circuits of other phases.

When the microcomputer (110) is activated and becomes operable, the program shown in the flowchart of FIG. 4 is started to initialize the system (that is, I / O).
Port setting, flag setting / reset, etc. are executed (step 1) to enter the main processing flow of overcurrent detection. Next, the A / D conversion circuit (100) is controlled to control the signal conversion circuit.
The signal of the effective value or the average value of the current corresponding to the phase in which the maximum current output from (90) flows is converted into a digital signal (step 2) and RA in the microcomputer (110) is converted.
Write to M (115) (Fig. 3) (A / D conversion process). Next, with respect to the input signal data written in the RAM (115), an operation of determining whether the value is an overcurrent value is executed (step 3). As a result, if it is determined that it is not overcurrent, the fourth
The heat storage routine in the figure is deviated, and the heat radiation routine described later is returned to the above-mentioned A / D conversion processing (step 2) again. If it is determined that there is an overcurrent, first the heat storage flag H
Is set (step 4), and a predetermined heat storage bit number is set every predetermined unit time by using a register in the CPU (111) or the RAM (115) to execute a timed operation according to the level of the input signal. Addition is performed (step 5). The predetermined number of heat storage bits is selected so as to realize a timed operation according to the operation characteristics of the static overcurrent detection device shown in FIG. Next, an operation of determining whether or not the added number of bits has reached a value corresponding to a predetermined time period is performed (step 6),
If the added bit number is not the value corresponding to the predetermined time period, the main flow is deviated and the process returns to the A / D conversion process (step 2). When the number of added bits reaches the value corresponding to the predetermined time limit, I / O port (11
6) Trigger the thyristor (120) via the output device (80)
Are driven (step 7). Whether or not it is an overcurrent is determined (step 3), and when it is determined that it is not an overcurrent, the process proceeds to (step 8). (Step 8) to (Step 11)
Up to the heat radiation routine is formed, and it is determined in (step 8) whether or not the heat storage flag H is set.
As a result, when the heat storage flag H is set, the predetermined heat radiation bit number is subtracted from the bit number added and counted in the heat storage routine every predetermined unit time. When the bit count value becomes 0 by this subtraction, the heat storage flag H is reset (step 9). When the heat storage flag H is not set, the process returns to the straight line A / D conversion process (step 2). Further, in (step 10), it is determined whether or not the count value of the bit subtracted in (step 9) is completely reset, and when it is not completely reset, the A / D conversion process (step 2) is directly performed. Return. When the bit count value is completely reset, the heat storage flag H is reset (step 11) and the process returns to the A / D conversion process (step 2). In this way, the timed operation along the characteristic curve shown in FIG. 5 is executed.

Although the processing circuit for the positive input signal is described in the above embodiment, it is needless to say that an equivalent circuit configuration is possible for the negative input signal. Although the method of performing the maximum phase discrimination using the average value of each phase is illustrated, the same function can be achieved even with the peak value. Further, the maximum phase discrimination function can be executed by the processing of the microcomputer.

[Effect] As described above, since the static overcurrent detection device according to the present invention has the maximum value discriminating circuit for each phase, the conventional static overcurrent detection device requires each phase. Only one expensive and complicated RMS value conversion circuit is required, fine adjustment at the phase signal level is not required, and the accuracy of RMS value conversion is improved due to the hysteresis characteristic. It is possible to provide a current detection device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the static overcurrent detection device according to the present invention, FIG. 2 is a concrete circuit diagram of the maximum phase discrimination circuit (400) shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the microcomputer (110) shown in FIG.
FIG. 6 is a diagram showing a flow chart of a program executed in the microcomputer (110), FIG. 5 is a characteristic diagram showing heat resistance amount characteristics and operation characteristics of electric paths and loads of a general static overcurrent detection device, FIG. FIG. 6 is a block diagram showing a conventional static overcurrent detection device. In the figure, (400) is a maximum phase discrimination circuit, (110) is a microcomputer, and (80) is an output device.

Claims (5)

[Claims] 1. A current detecting means for detecting a fault current generated in a plurality of phases of an alternating current circuit, and a secondary output signal corresponding to a current of each phase of the current detecting means, which has a maximum magnitude 2. A means for discriminating a phase including a secondary output signal and outputting only a secondary output signal of the phase, wherein a value obtained by multiplying a magnitude of the secondary output signal currently being output by a predetermined value is used as a discrimination threshold. If there is a phase in which the magnitude of the secondary output signal of each phase exceeds the discrimination threshold value, the maximum phase discriminating means discriminates the phase as a new maximum phase and outputs only the secondary output signal of the phase. A signal converting means for obtaining an effective value or an average value of the secondary output signal of the maximum phase discriminating means, a signal for receiving the secondary output signal from the signal converting means, performing arithmetic processing, and cutting off the circuit Static overcurrent equipped with arithmetic processing means for outputting Flow detector. 2. The static overcurrent detecting device according to claim 1, wherein the maximum phase discriminating means discriminates the maximum phase according to an average value of the secondary output signals of the current detecting means. . 3. The static overcurrent detection device according to claim 1, wherein the maximum phase discrimination means discriminates the maximum phase according to the peak value of the secondary output signal of the current detection means. . 4. The static type apparatus according to claim 1, wherein said arithmetic processing means is composed of a microcomputer, and said microcomputer performs arithmetic processing of the discrimination function of said maximum phase discrimination means. Overcurrent detection device. 5. The static overcurrent detecting device according to claim 2, wherein the current detecting means includes a direct current converting means.