JPH0628287B2 - Linear semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit in which circuit blocks having different signal frequencies and signal levels such as FM / AM tuners are formed on the same semiconductor substrate.

(B) Conventional technology Electronic equipment such as TV tuners and FA / AM tuners are
Since the audio signal is extracted from the F (Redio Frequency) signal, the frequency of the signal handled by each circuit block divided for each function is often different. For example, with an FM tuner only for domestic use in Japan, an RF signal of 76 to 90 MHz, an intermediate frequency signal of 10.7 MHz, and an audio signal of 20 to 20000 Hz, and each circuit block handling any signal of 20 Hz to 90 MHz. become.

An example of the FM / AM tuner is shown in FIG. In the figure, (1) is an FM front-end circuit for selecting an FM broadcast and frequency-converting it to an intermediate frequency, and (2) is an FM / IF for detecting an intermediate frequency signal (IF signal) to obtain an audio signal (AF signal). Amplifier circuit, (3) is, for example, Japanese Patent Publication No. 62-21
No. 461, a noise canceling circuit having a function as described above, (4) is a multiplex circuit for demodulating into L channel and R channel signals in the case of stereo broadcasting,
(5) is an AM that selects an AM broadcast and outputs an audio signal
It is a tuner circuit. For example, in the case of FM broadcast reception, the RF signal input from the antenna (6) and the oscillation frequency signal output from the local oscillation circuit of the FM front end circuit (1) are F
The IF signal is output from the FM front end circuit (1) by mixing with the mixer of the M front end circuit (1),
The IF signal is detected by the detection circuit of the FM / IF amplifier circuit (2) to output a composite signal from the FM / IF amplifier circuit (2), and the multiplex circuit (4) outputs L to the output terminal (7) respectively. It is configured to output channel and R channel audio signals. In addition, the FM having such a configuration
The tuner circuit is described, for example, in "'88 Sanyo Semiconductor Data Book Portable Audio Bipolar Integrated Circuit Edition", page 152, issued December 10, 1987.

By the way, in recent years, electronic devices are required to be smaller and have higher performance, and accordingly, the circuit of FIG. 5 is being integrated into one chip as much as possible. There are various demands for deleting, replacing, and adding specific circuit blocks to the circuit of FIG. Therefore, when trying to meet each request,
Since the specific circuit blocks are not always accommodated in the same occupied area, they have to be redesigned for each requirement, and there is a drawback that the requirement cannot be met immediately. Further, in the above FM tuner example, the FM front end circuit (1) handles a high frequency signal of several tens of MHz, so a signal with a common impedance by partially making the ground (GND) wiring or the power supply (V _cc ) wiring common interference,
There is a drawback that interference through a semiconductor substrate and interference due to a leak current due to a parasitic transistor effect are likely to occur and it is difficult to form one chip.

A conventional technique of this type is, for example, Japanese Patent Laid-Open No. 59-84.
There is a technique described in No. 542 (H01L 21/76). That is, the circuit blocks that are likely to cause interference are partitioned by the high-concentration isolation region that is connected to the semiconductor substrate, the ground wiring is extended to the surface of the isolation region, and the ground wiring is ohmic-contacted with the isolation region. This is a so-called suction electrode technology for sucking leak current. However, also in this example, when deleting, replacing, or adding the circuit block described above, it is necessary to redesign from the beginning,
It has the drawback of not being able to respond immediately to demand and requiring a long design time for model deployment. Even if the suction electrode is provided, it is impossible to completely eliminate the interference between the circuit blocks due to the potential difference caused by the impedance of the ground wiring.

(C) Problem to be Solved by the Invention As described above, the conventional bipolar type IC has a drawback that the pattern design cannot be dealt with immediately when the specific circuit block is deleted / replaced / added and the development period becomes long. Further, in the case where the high-frequency circuit is also integrated into one chip in accordance with the multifunctionalization of the IC, there is a drawback that interference easily occurs between the circuit blocks.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the semiconductor chip (11) is provided with a divided region (12) that crosses the center of the semiconductor chip (11) in a substantially straight line. Is divided into first and second regions ( 13 ) and ( 14 ) and the power line (15) and the ground line (16) are extended to separate each into a mat (18) of the same size. Power line (15) and ground line (16) on the split area (12)
And a plurality of separation areas are provided in the division area (12).
The dummy islands (21) surrounded by (24) are formed in a single layer or multiple layers.

(E) Operation According to the present invention, each circuit block is provided with an integer number of mats.
Since it is stored in (18), each mat (18) can be arbitrarily moved as a unit when deleting, replacing, or adding a specific circuit block. Therefore, the design change can be shortened because only the connection between the circuit elements housed in the changed mat (18) and the wiring between the mats (18) are changed. Further, by extending the power supply line (15) or the ground line (16), the dummy island (21) is provided in the divided region (12) which requires a relatively large occupied area, so that the high frequency can be achieved without increasing the chip size. It is possible to prevent interference due to leakage current when coexisting with a circuit.

(F) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a semiconductor integrated circuit of the present invention.
First, a divided region (12) is formed in the center of the semiconductor chip (11) so as to cross it in a substantially straight line, and the element forming region of the semiconductor chip (11) is divided into two regions of substantially the same size in the vertical direction.
The divided area (12) is an area for extending the wiring to be described later, and is an area in which no circuit element is formed.
The two regions divided by forming (12) are referred to as first and second regions ( 13 ) and ( 14 ), respectively. And the division area
A division line ( 17 ) in which a power supply _Vcc line (15) shown by a solid line in the figure and a ground line (16) also shown by a dashed-dotted line are extended in a pair in a direction orthogonal to the extending direction of (12). By arranging a plurality of the dividing lines ( 17 ) in parallel
The second area ( 13 ) and the second area ( 14 ) are divided into areas of substantially the same size, and each area is used as a mat (18). The size of the mat (18) is set so that an arbitrary fixed number of elements can be laid out.

On both sides of the mat (18), the V _cc line (15) and the ground line (16) forming the division line ( 17 ) extend in pairs,
By arranging them regularly, one of the mats (18)
The V _cc line (15) is extended to the side, and the ground line (16) is extended to the other side facing each other. The _Vcc line (15) and the ground line (16) extending to one side and the other side of the mat (18) supply operating power to the circuit elements housed in the mat (18).

The V _cc line (15) and the ground line (16) extending the partition line ( 17 ) are grouped according to the purpose or each circuit block, and extend on the divided region (12) and correspond to each other. It is individually connected to the _Vcc electrode pad (19) or the ground electrode pad (20). The combined _Vcc line (15) and ground line (16) are formed relatively wide in order to reduce the impedance of the wiring, so the divided area (12) in which a plurality of these wirings are arranged in parallel occupy a relatively large amount. Requires area.

V _cc line (15) and a ground line extending partition line (17) (16), V _cc line (15) and a ground line extending the divided area (12) above (16), and each mat (18 The connection wiring between the circuit elements in the parentheses is basically performed by the first layer wiring. Section lines ( 17 ) after the second layer wiring
It is mainly used to form signal transmission wirings between the mats (18) across the divided areas (12).

Incidentally, the divided area (12) sometimes extends in parallel with each division line ( 17 ). This is the _Vcc electrode pad (19) and the ground electrode pad (20) for the requirements of the package bin array.
If there is a positional restriction on the mats, or if there is a particular relationship between adjacent mats (18) or circuit function blocks, there is a need to separate each mat.
Provide between (18). In FIG. 1, between the mats D and E is the former reason, and between the mats M and N is the latter reason. The V _cc electrode pad (19) and the ground pad (2) provided near the ends of the divided regions (12a) extending in parallel are provided.
The _Vcc line (15) and the ground line (16) are routed from (0) respectively, and then the _Vcc line (15) and the ground line (16) are routed over the divided region (12) crossing the center of the semiconductor chip (11). Connected to the circuit element.

When the function-specific circuit block is stored in the semiconductor chip (11) in which the element formation region is divided into a number of mats (18) in this way,
Each circuit block is stored as follows.

First, since the mat 18 is designed to have a size capable of accommodating an arbitrary fixed number of elements, the circuit block is divided into the fixed number of elements. For example, the size of the mat (18) is 10
If 0 elements are to be stored and the circuit block has about 270 elements, three mats (18) are prepared and 100 elements each are divided. Of course, take into consideration capacitors that occupy a large area. Then, according to the above classification, each mat (1
8) Each circuit element is stored, and the NPN stored in the mat (18)
The connection wiring between circuit elements such as PNP transistor, diode, resistor, capacitor and the connection wiring between the element and _Vcc and the ground lines (15) and (16) are completed in the first wiring layer. After repeating the pattern design of all mats (18) by repeating this, the three mats (18) are arranged adjacent to each other,
By electrically connecting the mats (18) with the wirings of the second and subsequent layers, functional circuit blocks are constructed. Then, after storing all the circuit blocks in the mat (18), all the mats (18) are combined and the whole IC is designed by electrically connecting the circuit blocks by the second and subsequent wiring layers. To do.

According to such a configuration, by storing each circuit block in an integer number of mats, it is possible to design for each circuit block and divide the circuit block into a certain number of elements to create a mat (18).
Each design can be done. Therefore, parallel design is possible for each circuit block, and the design period can be greatly shortened. Further, the circuit can be changed for each circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

Then, as shown in FIG. 2, the semiconductor chip (11) is attached to the mat A.
Utilizing the area occupied by the split regions (12) for partitioning the first region consisting ~J (13) in a second region consisting of the mat K~T (14), the semiconductor chip along the dividing region (12) (11) A dummy island (21) extending to the peripheral portion is provided. Since this dummy island (21) is formed by the epitaxial region completely surrounded by the high concentration isolation region connected to the semiconductor substrate to which the ground potential is applied, each dummy island (21) is formed.
(21) is electrically independent of the others. In addition, as shown in FIG.
Area ( 13 ) is divided into a group of mats A to D and mats E to J (12a) and a second area ( 14 ) is divided into mats K to
Divided area (12a) divided into M and matte N to T groups
The dummy islands (21) also extend to the respective divided regions (12a).

The sectional structure of the dummy island (21) formed in the divided region (12) is as shown in FIG. (22) is a P-type semiconductor substrate, (23)
Is an N type epitaxial layer, and the dummy island (21) is formed by the N type epitaxial layer (23) surrounded by the P ⁺ type isolation region (24) as described above. The surface of the dummy island (21) is covered with an oxide film (25), and a plurality of V _cc or ground lines (15) and (16) extending the divided region (12) are provided in the first wiring layer on the surface. The mats (18) extend in parallel with each other, and further on the second wiring layer thereabove via the interlayer insulating film (26).
The signal transmission wiring (27) for connecting the two or a portion of the _Vcc or ground wiring (15, 16) extends.

According to such a configuration, the first area and the second area divided by the divided area (12) are divided.
Since the regions ( 13 ) and ( 14 ) are separated from each other by the area occupied by the divided region (12), the resistance due to the layer resistance (28) of the substrate (22) and the layer resistance (29) of the epitaxial layer (23). By increasing the component, the coupling between the first region ( 13 ) and the second region ( 14 ) can be roughened. In addition, if the dummy island (21) is made into a multiple structure by utilizing the occupied area of the divided region (12), in addition to the resistance component (29) formed by the layer resistance of the epitaxial layer (23), the isolation region (24) is formed. Since a plurality of potential barriers are formed by the PN junction formed by the P-type region and the N-type region of the dummy island (21), the resistance component can be increased, and the first and second regions ( 13 )
The bond of ( 14 ) can be made coarser. Further, the potential barrier is P
It can be considered as a junction capacitance (30) due to an N junction, so the _Vcc line (15) extending above the division region (12) is used to form a dummy island (21) via the N ⁺ type contact region (31). By applying the power supply potential _Vcc , the dummy island (21) can be grounded in an alternating current manner, the junction capacitance (30) can be increased, and the resistance component can be increased. In the example of FIG. 3, the dummy island (21) has a triple structure, _Vcc is applied to the central dummy island (21), and the dummy islands (21) on both sides are in a floating state in which no potential is applied. Generally, when the dummy island (21) has a multiple structure, the coupling between the first and second regions ( 13 ) and ( 14 ) can be roughened, so that the occupation area of the isolation region (24) is divided as the minimum line width of the process. Form as many layers as possible within the area occupied by the region (12).

As described above, the dummy island (21) is formed in the divided area (12).
Since the coupling between the first and second regions ( 13 ) and ( 14 ) can be roughened by forming the, the FM / AM tuner as shown in FIG. 5 is formed on the semiconductor chip (11) by utilizing such an advantage. An example will be described below.

In FIG. 1 or 2, the AM tuner circuit (5) block is attached to the four mats (18) of mats A to D and mats E to
FM / IF amplifier circuit (2) block on 5 mats (18) of I, other (optional) circuit block on 1 mat (18) of mat J, and 3 mats of mats K to M (1
8) FM front end circuit (1) block is mat N
The noise canceling circuit (2) block is housed in each of the three mats (18) to P, and the multiplex circuit (4) block is housed in each of the four mats (18) of mats Q to T. .

The FM front end circuit (1) stored in the mats K to M is
An RF signal tuned by an antenna (6) and a tuning circuit (not shown) is input, and the RF signal and the local oscillation frequency signal generated by the local oscillation circuit are mixed by a mixing circuit to
It has a function of frequency-converting into an intermediate frequency signal of 0.7 MHz and outputting. Since this circuit handles a signal of a very small level of several microvolts (μV) to a signal of several volts (V), it is an extremely disliked circuit for interference signals from other circuit blocks. Since the local oscillator circuit oscillates itself and emits unnecessary radiation, it is a circuit that should be separated from other circuit blocks as much as possible.

On the other hand, FM / IF amplifier circuit (2) stored in mats E to I
Has a function of amplifying and limiting the amplitude of the intermediate frequency signal by a limiter amplifier circuit, and detecting it by a detection circuit to demodulate it into a composite signal. Since such a circuit handles a frequency signal of 10.7 MHz, which is relatively close to the frequency handled by the FM front-end circuit (1), and further handles a signal of a large amplitude level by amplifying it, the FM / IF amplifier circuit (2)
When the leakage current from the RF front end circuit (1) reaches, the RF signal is erased by mutual signal interference,
In particular, when the input level is extremely low, the circuit becomes unstable, and when it is significant, oscillation occurs. Therefore, the combination of the FM front end circuit (1) and the FM / IF amplifier circuit (2), especially the local oscillator circuit and the limiter amplifier circuit, is a combination in which mutual separation must be made strong.

On the other hand, the multiplex circuit stored in the mats Q to T (4)
Is the sum signal (L + R) and the difference signal in the composite signal
(LR) is also included in the composite signal.
38KHz produced in response to a KHz stereo pilot signal
It has a stereo demodulation function of separating left and right stereo signals (L and R) using a switching signal. Since this circuit utilizes the switching operation of the transistor to generate the 38 KHz switching signal, it is easy to generate switching noise in accordance with the operation. For example, a phase comparator as a circuit for generating the switching signal,
The case where a PLL (phase locked loop) circuit including a low-pass filter, a voltage-controlled oscillator, and a plurality of frequency dividers is used is equivalent. Therefore, if possible, FM
It is a circuit that should be kept away from the front end circuit (1) and the FM / IF amplifier circuit (2).

Also, the noise canceling circuit (3) stored in the mats N to P
Has a function of removing pulse noise when it is superimposed on the composite signal. This circuit neither handles high frequency signals nor generates switching noise.

Furthermore, AM tuner circuit (5) stored in mats A to D
Has a function of selecting an AM broadcast and outputting an audio (AF) signal. Generally, the time of FM broadcast reception and the time of AM reception are completely switched by an external control signal, and the frequency is around several hundred KHz, so the AM tuner circuit (5) and FM
It can be considered that there is no signal interference with the front end circuit (1) or the FM / IF amplifier circuit (2).

According to such a configuration, the FM front end circuit (1) and the FM
Since the IF amplifier circuit (2) is formed in the mat (18) of the first and second areas ( 13 ) and ( 14 ) respectively, both can be separated by the distance of the divided area (12) and the dummy Due to the impedance increase due to the island (21), both epitaxial layers (2
The coupling via 3) can be made even coarser. Therefore, FM
The front end circuit (1) and the FM / IF amplifier circuit (2) can be integrated into one chip by preventing signal interference with each other. Further, since the multiplex circuit (4) which easily generates switching noise sandwiches the division area (12) and the dummy island (21) with respect to the FM / IF amplifier circuit (2), the FM front end circuit (1 ) For the noise cancellation circuit
(3) Since the block and the dummy island (21) are sandwiched between them,
Coupling with the respective circuits can be roughened to prevent signal interference.

By the way, the FM front end circuit (1) and the FM I
In addition to the relationship with the F amplifier circuit (2), the adjacent mat (18)
In the meantime, interference occurs between the circuit elements formed in the mat (18) and the like through the substrate (22). This interference is mainly caused by the leak current to the substrate (22), and the circuit elements that easily leak the leak current are capacitors, NPN / PNP transistors with saturation operation, and laterals based on the N-type epitaxial layer (23). I using PNP transistor and lateral PNP transistor as injector
IL and the like are given, and the potential of the substrate (22) is raised not only to the adjacent circuit elements but also to the distant circuit elements to make the circuit operation unstable.

As shown in FIG. 3, the isolation region (2
4) It is dealt with by the suction electrode (32) which makes ohmic contact with the surface. That is, as shown in FIG. 4, contact holes are formed between the circuit elements or between the circuit element groups in which it is predicted that interference will occur in the immediate vicinity of the circuit elements that easily leak the leak current.
(33) is an ohmic contact via a partition line (1
It is connected to the ground line (16) forming 7 ) and grounded. Further, the ground line (16) forming the partition line ( 17 ) itself is also used as the suction electrode (32) to prevent interference between the mats (18) and prevent an increase in chip size.

The ground line (16) to which the drain electrode (32) is connected is divided or shared depending on the magnitude of the leak current leaked and whether or not the ground line (16) has a common impedance. Therefore, a plurality of ground lines (16) extend on the divided area (12). For example, in FIG. 4, the matte E has the capacitor elements constituting the MF / IF amplifier circuit (2) arranged centrally, and the substrate (22)
Since it is predicted that the leakage to the ground will be extremely large, the ground line (16) forming the partition line ( 17 ) itself is used as the suction electrode (32) and the entire mat E is sucked out (3).
Extend the ground line (16) so that it is surrounded by 2), and further extend the outer periphery of the chip (11) so that the ground electrode pad (20)
Connect to. The suction electrode (32) in the area of the mat E is for preventing the above capacitor elements from interfering with each other. The suction electrode (32) in the area of the mat G is provided in the immediate vicinity of the circuit element which easily leaks the leak current. Since the suction electrode (32) has a small absolute value of the leak current, Ground line (16) that provides the ground potential for circuit operation
Have in common with. The circuit elements formed on the mat F and the mat G allow the common impedance in terms of function, and the absolute value of the leak current is not so large, so that these ground lines (16) are divided into the divided regions (12). )
Put them all together and connect to the ground electrode pad (20).

(G) Effect of the Invention As described above, the present invention is based on the mat (18), and each circuit block is housed in an integer number of areas of the mat (18). Therefore, pattern design can be performed for each mat (18). By combining the mats (18) whose design has been completed, there is an advantage that the layout of the entire IC can be arbitrarily realized. Also, the mat (1
8) There is also an advantage that parallel design can be performed for each. Therefore, the design period of the entire IC can be shortened, and when designing models with different circuit functions, only the changed mat (18) needs to be designed, and the remaining mat (18) has the reliability of the previous model. Since it can be reused while maintaining the above, there is an advantage that the design period required for model development can be greatly shortened.

Then, the V _cc line (1) for forming the mat (18) and for supplying operating power to the circuit elements housed in the mat (18)
5) and the area occupied by the divided region (12) extending the ground line (16) is used, and the dummy island (21) is provided in this portion, so that the occupied area can be effectively used and the divided region (12 ) The first and second areas ( 13 )
Coupling of ( 14 ) through the substrate (22) can be rough. For that reason,
When forming circuit blocks on the same chip (11) whose frequency and signal level are different from each other and are likely to cause signal interference, separate these circuit blocks into first and second regions ( 13 ) ( 14 ). The combination of the mats (18) has an advantage that a high-performance IC in which mutual signal interference is prevented can be realized. Also,
FM front end circuit (1) and FM
-By integrating the IF amplifier circuit (2) into a single chip, there is also an advantage that a cheaper and higher-performance FM tuner can be provided.

Further, since the drain electrode (32) is provided near the circuit element in the mat (18) where leak current is likely to occur, the leak current to the substrate (22) can be immediately drained and the adjacent circuit element Interference can be prevented.

Further, by extending the suction electrode (32) between the adjacent mats (18), the suction electrode (32) in the mat (18)
It is possible to absorb the leak current that cannot be completely removed by the method and the leak current from other circuit elements, and prevent the interference between the adjacent mats (18). Further, by using the ground line (16) for forming the partition line ( 17 ) as the suction electrode (32), there is an advantage that the occupied area can be efficiently used.

[Brief description of drawings]

1 and 2 are plan views for explaining the present invention, FIGS. 3 and 4 are cross-sectional views and a plan view of main parts for respectively explaining the present invention, and FIG. 5 is FM / It is a circuit diagram for explaining an AM tuner circuit. (12) is a divided area, ( 13 ) ( 14 ) is the first and second areas, and (15) (1
6) is _Vcc and ground line, (18) is mat, (21) is dummy island, (24) is P ⁺ type isolation region, and (32) is suction electrode.

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04B 1/08 E 7240-5K

Claims (2)

[Claims] 1. A division region that substantially divides the semiconductor chip into a first region and a second region in the center of the semiconductor layer of the semiconductor chip, and is positioned in the first region and the second region, Arrangement regions (mats) of semiconductor elements formed in the semiconductor layer, which are formed of a plurality of shapes having substantially the same size, and power supply lines provided on one side and the other side of the arrangement region, A linear type semiconductor integrated circuit in which a semiconductor element of a linear electronic circuit including a ground line and a plurality of electronic circuit blocks whose functions are substantially different in circuit size is formed in the arrangement area (mat). Therefore, all the semiconductor elements of the electronic circuit block divided by the function are obtained by dividing the total number of semiconductor elements of the electronic circuit block in units of the arrangement area (mat). Are substantially formed in a plurality of arrangement areas (mats), and the power supply line and the ground line extending to the power supply pad and the ground pad provided around the semiconductor chip are formed in the divided area. A dummy island made of the semiconductor layer, which is provided and is surrounded by an isolation region of a conductivity type opposite to that of the semiconductor layer formed in the semiconductor layer, is provided along the divided region up to the peripheral portion of the semiconductor chip. And the linear semiconductor integrated circuit. 2. A dividing region for substantially dividing the semiconductor chip into a first region and a second region, and a dividing region positioned in the center of the semiconductor layer of the semiconductor chip, and the first region and the second region. Arrangement regions (mats) of semiconductor elements formed in the semiconductor layer, which are formed of a plurality of shapes having substantially the same size, and power supply lines provided on one side and the other side of the arrangement region, A linear type semiconductor integrated circuit in which a semiconductor element of a linear electronic circuit including a ground line and a plurality of electronic circuit blocks whose functions are substantially different in circuit size is formed in the arrangement area (mat). Therefore, all the semiconductor elements of the electronic circuit block divided by the function are obtained by dividing the total number of semiconductor elements of the electronic circuit block in units of the arrangement area (mat). Are substantially formed in a plurality of arrangement areas (mats), and the plurality of electronic circuit blocks include at least a first circuit block having a high frequency and a second circuit block having a different function and frequency. The first circuit block is formed in one of the first or second regions, the second circuit block is formed in the other of the first or second regions, The power supply line and the ground line extending to the power supply pad and the ground pad provided around the semiconductor chip are provided, and the power supply line and the ground line are surrounded by a separation region of the opposite conductivity type to the semiconductor layer formed in the semiconductor layer. A linear semiconductor integrated circuit, wherein a dummy island made of the semiconductor layer is provided along the divided region up to the peripheral portion of the semiconductor chip.