JPH0691226B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a pattern layout that allows easy model deployment so as to meet the demands of custom ICs. The present invention also relates to a semiconductor integrated circuit having a surge protection device that prevents dielectric breakdown.

(B) Conventional technology Generally, as disclosed in Japanese Patent Laid-Open No. 59-84542 (H01L21 / 76),
A semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate has a configuration shown in FIG.

FIG. 8 is a schematic plan view of the semiconductor chip (201),
a to f indicate circuit blocks. These circuit blocks have different frequencies and signal levels to be handled, and also have different functions.

This circuit block is formed in an N type region (203) on a P ⁻ type semiconductor substrate (202) as shown in FIG. 9, and each circuit block is adjacent to the periphery of a high concentration P ⁺ type region. (20
It is divided by 4). Here, it is shown by block b and block c.

The P ⁺ type region (204) for this partition has one end in contact with the P ⁻ type semiconductor substrate (202) and the other end ohmic-connected to the ground line (206) through the oxide film (205) on the semiconductor surface. To be done.

The ground line (206) is gathered from each block in the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, the power supply line (V _CC ) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to the power supply bonding pad, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions, the number of elements existing in the block is different and the block sizes are different.

(C) Problems to be Solved by the Invention As described above, since the circuit blocks a to f have different sizes, in order to efficiently accommodate all of these circuit blocks in the semiconductor chip (201), the size of each circuit block is large. However, there is a problem in that they interact with each other, making integration on the same chip difficult.

Further, when the circuit block a is deleted and another circuit block a'having improved characteristics is inserted, or a circuit block g having another function is added to the circuit block configuration of FIG. Since the size of is different, it was necessary to recreate it with all the patterns.

Therefore, in recent years, when the life of the product has become extremely short, if the user wants to incorporate a unique circuit desired by a user into a certain chip, the user desires a short delivery time, but the circuit is short. It had a problem that it needed a very long delivery time to recreate the pattern.

On the other hand, with the miniaturization of semiconductor chips, destruction due to static electricity has become an important issue. This breakdown method is that when an electrostatic surge is applied to the PN junction in the opposite direction, charge carriers are accelerated at this junction, causing avalanche collapse. It is considered that the crystal lattice is destroyed because the collapse concentrates on the poles of the junction.

As a measure to prevent this destruction, a measure as shown in Fig. 10 is considered. However, when trying to realize this circuit, there is a problem that the arrangement and connection on the substrate becomes complicated and the design becomes complicated.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and for each block region in which all electronic circuit blocks are formed, a plurality of pads (90) derived from the electronic circuit blocks are provided. It is provided on the side of the block area (91) corresponding to the periphery of the chip, and the plurality of pads (90) and the plurality of pads and the block area (9
It was solved by installing a protection diode between 1) and
Further, the partition line ( 5 ) divides the upper surface of the semiconductor chip (1) into a large number of mats having substantially the same size, and accommodates a plurality of electronic circuit blocks having different functions in one or more integer number of mats. It is something that can be solved.

(E) Operation According to the present invention, a plurality of pads of this electronic circuit block are provided for each block area, and a protection diode is formed between the block area and the plurality of pads and a lower layer area of the pad. . Therefore, the pattern layout in the block area is hardly affected, and the layout can be arranged in an orderly manner. On the other hand, by dividing the upper surface of the semiconductor chip (1) into a large number of mats having substantially the same size by the division line ( 5 ) and accommodating a plurality of electronic circuit blocks having different functions in an integral number of mats, an electronic circuit It becomes possible to design for each block, and to divide the electronic circuit block by a fixed number of elements to design for each mat. Therefore, it is possible to divide each electronic circuit block for parallel design, and it is possible to significantly reduce the design period.
Further, the circuit can be changed for each electronic circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

(F) Examples Examples of the present invention will be described below. The present application has the same effect in the semiconductor integrated circuit as shown in FIG. 8 and the semiconductor integrated circuit as shown in FIG. 3 using the mat division. Therefore, the semiconductor integrated circuit described here uses mat division.

Therefore, first, the mat division will be described below with reference to FIG.

The first and second semiconductor chips (1) have substantially the same shape by using the divided regions (2) indicated by the chain double-dashed lines.
Area (3), (4), and each area (3),
(4) is divided into mats A to J and K to T. A
The mats J to K and K to T are divided by a partition line ( 5 ) in which a power line indicated by a solid line and a ground line indicated by a dashed line are adjacently extended in parallel.

Regarding the arrangement of the power supply line and the ground line forming the division line ( 5 ), the power supply line indicated by a solid line is provided on the left side of each of the mats A to J and K to T, and the ground line indicated by a dashed line is provided on the right side. Therefore, only the partition line ( 5 ) at both ends is formed on one of the power line and the ground line,
The middle section line is made up of both. Each mat A
Power lines and ground lines adjacent to J, K, and T are integrated in each mat to supply power to the circuit blocks.

The power supply line and the ground line of each partition line ( 5 ) are the third power supply line (6) and the second power supply line (7), the third ground line (8) and the second power supply line (7), which are indicated by the three-dot chain line. The third and second power supply lines (6) and (7) and the third and second ground lines (8) and (9) are connected in a comb shape so as to face the ground lines (9), respectively.
Are led to the power supply pads V _CC1 and V _CC2 and the ground pads GND1 and GND2 among the pads provided around the pellet.

As will become apparent later, the mats K to M have
Separate from the pads, V _CC3, V _CC4, GND3, using GND4, and each power supply line, ground line, and the second and third power supply line (7), (6), second and Three
The ground lines (9) and (8) of (1) are, in principle, realized by one-layer wiring of the two-layer wiring.

Each of the mats A to J divided by the division line ( 5 ) described above
K to T are formed in a shape having substantially the same size, and specifically, the width is set so that six NPN transistors are arranged, and the length is a fixed number of elements which is easy to design, for example, It is set so that about 100 elements can be laid out.
The size of this mat can be arbitrarily selected according to the number of elements that can be easily designed by an electronic circuit block to be integrated into an IC.

The circuit elements integrated in the mat consist of transistors, diodes, resistors and capacitors,
Separated by PN separation, the connection of each element is connected by the first electrode layer of the two-layer wiring, and is exceptionally crossed over by the second electrode layer.

Next, with reference to FIGS. 4A and 4B, the circuit elements integrated in the mat and the partition line ( 5 ) will be specifically described.

FIG. 4A is an enlarged top view of the vicinity of the mat B. The division line ( 6 ) indicated by the alternate long and short dash line on the left is mat A and mat B.
The partition line ( 5 ) provided between the mats B and C, and the partition line ( 7 ) indicated by the alternate long and short dash line on the right is the partition line ( 5 ) provided between the mat B and the mat C. The transistor (8), the diode (9), the resistor (10) and the capacitor (11) shown by the dotted line are integrated between the division lines ( 6 ) and ( 7 ). Although these elements are rough in the drawing, they are actually densely integrated. The wiring between the elements in the mat is substantially formed by the first electrode layer (12) indicated by the alternate long and short dash line, and the wiring between the mats A and B and between the mats B and C,
For example, signal lines and feedback lines are formed by the second electrode layer (13) shown by solid lines. The first and second electrode layers (12) and (13) are connected to each other by the contact regions shown by "x".

4B is a sectional view taken along the line AA ′ in FIG. 4A.
An N type epitaxial layer (15) is laminated on a P type semiconductor substrate (14), and this epitaxial layer (15)
A P ⁺ type isolation region (16) reaching the semiconductor substrate (14) from the surface is formed, and a large number of island regions are formed. NPN transistors (8), diodes (9), resistors (10), capacitors (11), etc. are formed in the island region (17), and the collector region (18) of the NPN transistor (8) and the semiconductor are formed. An N ⁺ type buried region (19) is formed between the substrate (14) and the substrate. A silicon oxide film (20) is formed on the surface of the epitaxial layer (15) by, for example, a CVD method, and a first electrode layer (12) is formed on the silicon oxide film (20). . Also, to cover the first electrode layer (12),
For example, an insulating film (21) such as PIX is formed, and this insulating film (2
A second electrode layer (13) is formed on the first layer. The power supply line (22) and the ground line (23) are provided on the separation region (16), and the ground line (23)
Is in ohmic contact with the isolation region (16) to stabilize the substrate potential.

More specifically, 10 mats A to J are formed in the first area (3), and 10 mats K to T are formed in the second area (4). Substantially the same space where approximately 100 elements can be integrated is set, and each mat is divided by a division line ( 5 ).

In the above 20 mats, a one-chip IC for AM / FM stereo tuner shown in FIG. 6 is formed. FIG. 6 is a block diagram for explaining this electronic block circuit. The FM front end block (24), FM-IF block (25), noise canceller block (26), multiplex decoder block (27), AM tuner block. (28)
It is composed of a total of five electronic circuit blocks. Although each circuit block is well known, its function will be briefly described.

First, the FM front-end block (24) is the part for selecting the FM broadcast and receives the FM broadcast signal of several tens of MHz to several hundreds of MHz.
It is used for frequency conversion to an intermediate frequency signal of 0.7 MHz, and has about 250 elements, so it is integrated in a mat of K to M. Next, the FM-IF block (25) amplifies this intermediate frequency signal and then detects it to obtain an audio signal. Since it has about 430 elements,
It is integrated in the I mat. The noise canceller block (26) is for removing pulse noise such as ignition noise. Since it has about 270 elements, it is integrated in the N to P mats. Further, the multiplex decoder block (27) is a block for stereo demodulating a stereo signal, and has about 390 elements, so that it is integrated in a mat of Q to T. Lastly, the AM tuner block (28) is the channel selection part of AM broadcasting, which converts the AM broadcasting signal received by the antenna to an intermediate frequency (450KHz) and detects it to obtain an audio output.
Since it has individual elements, they are integrated in the mats A to D.

Further, in FIGS. 7A, 7B and 7C, an AM tuner block (28) and a front end block (2
4) shows a further block diagram of the FM-IF block (25) and the multiplex decoder block (27).

First, the local oscillation circuit (OSC) (29) in the AM tuner block (28) of FIG. 7A is on the mat A, and the mixing circuit (MIX).
(30) on mat B, automatic gain control circuit (AGC) (3
1), the high frequency amplifier circuit (RF) (32) and the intermediate frequency amplifier circuit (IF) (33) are on the mat C, and the detection circuit (DET) (3
4) is substantially integrated into the mat D, the third power supply line indicated by the third three-point power supply pad V _CC1 was Zaisa 4 extends in the octopus leg-shaped than as Figure dashed line (35), (36), V _{CC to} the first power supply line (39) of the mats A to D via (37) and (38)
Is being supplied. Further, the ground pad GND1 has three octopus-shaped electrodes (40) provided between the mat M and the mat N.
Is connected to second ground lines (41), (42), (43) indicated by the three-dot chain line on the one-end divided region (2) via the respective second ground lines (41), (42). , (43) is A
To D mats are connected to the first ground line (44).

Next, the high frequency amplifier circuit (45) and the mixing circuit (46) of FIG. 7B.
The front end block (24) composed of the local oscillation circuit (47) and the local oscillation circuit (47) handles a signal of an extremely small level of several μV, and therefore other circuit blocks, particularly the FM-IF block (2
Dislike the interference from 5), and the local oscillator circuit (47) in this block oscillates itself, generating unnecessary radiation. Therefore, it is necessary to separate it from the FM-IF block (25),
Another power supply V _CC3 for C block dislike the most interference, V _CC4, GND
3, GND4 is used.

That is, KM which is diagonal to the FN-IF block (25)
The local oscillation circuit (47) is integrated on the mat K, which is the most corner, and the other pad V _{CC4 is arranged on} both sides of the local oscillation circuit (47).
A first power supply line (48) and a ground line (49) are provided through and GND4. The other L and M mats are provided with respective first power supply lines and ground lines (50) and (51) through V _CC3 and GND ₃ .

On the other hand, an FM-IF block (25) including an intermediate frequency amplification circuit (52), a detection circuit (53), an S meter (54), etc.
Are integrated in the mats E to I, and the detection circuit (53) is in the mat I, the S meter (54) is in the mat G, and the limiter circuit and the mute circuit in the intermediate frequency amplifier circuit (52) are , E, F and G mats are virtually integrated.

Here, a limiter circuit having a very high gain of 80 to 100 dB and a detection circuit (53) having a large signal level, and the limiter circuit and an S meter (54) having a large signal level generate oscillation due to feedback, and the detection circuit (53) and S Since the characteristics of the meter (54) are deteriorated due to mutual interference, the first power supply line (55) of the mats E, F, G is connected to the third power supply line (37) indicated by the one-dot chain line. The first power line (56) for H and I is
It is connected to one third power supply line (36). The mat J has an optional circuit from the user integrated therein, and the first power supply line (57) is also connected to one third power supply line (35).

The first ground line (58) indicated by the alternate long and short dash line on the mats E to J extends from the ground pad GND1 in a octopus-like shape and is connected at one end to the second ground line (4).
1), (42) and (43) are connected in the same manner as described above.

Then, the DC amplifier circuit (59), the decoder circuit (60) of the multiplex decoder block (27) of FIG. 7C,
The lamp driver circuit (61) is on the mat Q and mat R,
In addition, the phase comparison circuit (62), low-pass filter circuit (6
3), the voltage controlled oscillator (64), the frequency dividing circuit (65), etc. are substantially integrated on the mat S and the mat T. The electrode was Zaisa three extending from the power supply pad V _CC2 in octopus form (6
6), (67), (68) are AM tuner blocks (28)
And the FM-IF block (25), and the divided area (2)
One end is connected to the second power supply lines (69), (70), (71) above. And one is for mats Q and R, one is for mats S and T, and one is for noise canceller block (2
6) It extends to the mat of N to P which becomes.

On the other hand, the ground pad GND2 is connected to the three third ground lines (72), (73) and (74) in an octopus-like shape, and the mats of N to P, the mats of Q and R, Extends to S and T mats.

In addition, pad V is used to prevent mutual interference between blocks.
_CC1 and V _CC2 and pads GND1 and GND2 are used separately, and pads V _CC1 and V _CC2 are connected to the lead (75).
D2 is connected to the lead (76). This is the pad V _CC1
Is prevented from being directly transmitted to the pad V _CC2 , and the impedance of the thin metal wire is lowered by using two thin metal wires. Therefore, pulse noise etc. that entered the lead is not amplified through the impedance,
Voltage fluctuations can be prevented.

As described above, the partition line ( 5 ) composed of the first power supply line and the first ground line A to J,
The mats K to T are divided. Further, since the first power supply line and the first ground line are formed substantially in a comb shape, the space between the mats and the peripheral space can be effectively utilized, and the pad V _CC1 around the chip (1) can be effectively used. , GND
1 and GND2 can be connected at the shortest distance.

Next, countermeasures against interference between the FM front end (24) and the FM-IF block (25) will be described. In the past, it was a problem on the set board because each individual IC was used, but this time this interference became a problem because it was one chip, but it is solved by the following measures.

First, as mentioned above, the FM front end block (24)
Since it handles signals of a very small level of several μV, it dislikes interference from other circuit blocks, especially the FM-IF block (25), and the local oscillator circuit (47) built in this block itself oscillates. However, in order to generate unnecessary radiation,
It is necessary to separate from other blocks or provide another power source.

For these reasons, first of all, with the FM front end block
The FM-IF block was provided diagonally, and the local oscillator circuits in this block were integrated on the mat K and separated. Next, AM tuner block (28) and FM-IF block (2
5) The FM front end block (24) can be set by widening the partition line width between the FM front end block (24) and the noise canceller block (26), that is, the mat D and the mat E, and the mat M and the mat N. Keep away from other blocks, especially the FM-IF block (25). Further, between the mat D and the mat E and between the mat M and the mat N, an electrode (6 which extends from the power supply pad V _CC2 to the second region (4) is provided.
6), (67), (68) and an electrode (40) extending from the ground pad GND1 to the first region (3) are provided, and a second power supply line (69) is further provided on the divided region (2). ), (70), (7
1) and second ground lines (41), (42), (43) are provided. Therefore FM front end block (24)
Is separated from the adjacent FM-IF block (25), AM tuner block (28) and noise canceller block (26), and the power supply lines (66), (67), (68) prevent unnecessary radiation, At least one of the ground lines (40)
Since the book is in contact with the isolation region (16), it can absorb the substrate current and prevent interference.

The local oscillator circuit (47) in the FM front end block (24), since hate interference, provided separately the power pads V _CC4 and ground pad GND4, circuit outside the power supply pad V
Supplied on _CC3 and ground pad GND3.

Further, the FM-IF block (25) has a limiter circuit for removing the AM part of the FM signal, and this circuit is integrated with the mat E and the mat F. The capacitor in this limiter circuit leaks to the substrate, and this leak current flows to the FM front end, causing malfunction. Therefore, the capacitors are collectively put on the mat E, and are concentratedly sucked out by the first ground line (77) of the partition line ( 5 ) on the left side of the mat E. Furthermore, this first ground line (77)
Extends to the outer periphery of the area where the FM-IF block (25), the multiplex decoder block (27) and the noise canceller block (26) are formed, and also leaks the leak current generated from these. Similarly, a ground line (78) is provided around the left half of the chip (1). Also, due to wiring, the third power supply run-in (35),
(36), (37), (38), second power supply lines (69), (70), (71) and second ground lines (41), (42), () on the divided area (2). 43) and the like cross over through the through hole indicated by the black circle and the second electrode layer (79) indicated by the dotted line. In particular, the AM tuner block (28) does not work at the same time as the external block circuit, so the AM tuner block (28) and FM-IF block (2
5) share one pad V _CC1 and therefore cross over. The same applies to the ground pad GND1.

The above configuration is shown in FIG. The one indicated by the chain line is 1
The electrode formed in the second layer, which is shown by the solid line, is the second layer electrode. The area indicated by X is a through hole. Also, since the two blocks do not work at the same time, the power supply line and the ground line are shared, and the pattern is pad V
_Since the electrodes from _CC1 and GND1 to the through hole are shared, the area occupied by the electrodes can be reduced.

An example of the characteristic point of the present invention will be described. For example, if the AM tuner block (28) is unnecessary, four mats that will be the multiplex decoder block (27) are integrated as they are in the mats A to D, and the mats I and J, for example, are mated in the remaining mats Q and R. To be integrated. Therefore, since the I, J, S, and T mats are redundant, if this mat is deleted, the mats can be neatly housed in a rectangular chip. Here, the first layer wiring in the mat is used as it is,
Only wiring between mats and wiring between blocks need be considered.

In addition, when partly improving the FM-IF block (25), for example, it is sufficient to take out only the mat F, which is the improvement part, and improve it.
Other mats E, G, H can be used as they are. Also, when adding another block that is an option for the user,
You can use all the mats as they are and add as many mats as you need for this block.
Is the mat for this option.

That is, since mats having the same size are formed in a matrix, replacement, addition, and deletion are very easy.

The above is the configuration of mat division. Next, the structure for protection against surges of the present application will be described.

Basically, it has the configuration of the circuit diagram shown in FIG. FIG. 1 shows how this circuit is constructed.

Pads (90) ... (90) provided around the semiconductor chip (1) and used for input / output signals are provided around the semiconductor chip (1) for each electronic circuit block. For example, in the block area (91) of the mat A to mat D which is the AM tuner block (28), a total of 11 pads (90) ... (90) are provided on the left side and the upper side of the block area (91). Has been. Therefore, for convenience of description, the entire area in which the electronic circuit block is formed is named a block area.

As you can see from Figure 3 and Figure 5, the pad (90)… (9
0) and the third power line (35), (36), (37), (3
8) The inside of the lower layer substrate is a region where nothing is formed and there is practically much waste. Therefore, in the present application, the N-type first diffusion region (92) is provided between the series of pads (90) ... (90) and the block region (91), and the pads (90).
The second diffusion region (93) of N-type is provided in the lower layer of 0), and 11 P-type second diffusion regions (93) are provided in the first diffusion region (92) of N-type corresponding to each pad. Three diffusion regions (94) were provided.

The first to third diffusion regions (92), (93), (94)
Are the cathode and diode of diode D ₁ in Fig. 10, respectively.
It becomes the cathode of D ₂ and the anode of diode D ₁ . Here, the anode of the diode D ₂ serves as a P-type semiconductor substrate.

FIG. 2A is a partially enlarged top view of the block area (91) of the AM tuner block of FIG. 1, showing pads (90) ... (90) and third power supply lines (35), (36). This is a more detailed representation of the space between. Indicated by dotted line (9
2), (93), and (94) are the first to third diffusion regions, respectively, and (35) and (36) indicated by the alternate long and short dash line are the third power supply lines.

In the second diffusion region (93), there is an N ⁺ type contact region (95) shown by a dotted line, and this contact region (9
There is a first electrode (96) indicated by a chain line extending to the third diffusion region (94) through the above 5). A pad (90) shown by a solid line is formed at one end of the first electrode (96), and a second electrode (97) shown by a solid line is formed at the other end to connect to the electronic circuit block. . (98), (99),
The cross mark (100) indicates the contact between the first electrode (96) and the pad (90), the third diffusion region (94) and the first electrode (9).
6) Contact with the first electrode (96) and the second electrode (9)
7) shows contact with. The cross mark (101) indicates the contact between the third electrode line (35) and the first diffusion region (92). Also shown by the dotted line (102)
Is an N-type dummy island surrounding the N-type second region (93).

Next, description will be given with reference to FIG. 2B which is a sectional view taken along the line AA ′ in FIG. 2A.

An N type epitaxial layer (15) is laminated on a P type semiconductor substrate (14), and a P ⁺ type epitaxial layer (15) reaching the semiconductor substrate (14) via the N type epitaxial layer (15) is formed. There is a separation area (16). Surrounded by the isolation region (16), the first and second diffusion regions (92) and (93) and the dummy island (102) are formed.

FIG. 2C shows pads (90) corresponding to the mats N to P (9
It is a figure showing between 0) and the 3rd grand lines (72), (73), and (74). Basically the same as in FIG. 2A, except that a part of the first diffusion region (92) projects into the block region, and the contact (103) shown by a cross connects to the first power supply line. There is.

(G) Effect of the Invention As is apparent from the above description, firstly, the pad (90) ...
The structure as shown in FIG. 10 can be achieved by effectively utilizing between the (90) group and the pad group and the power supply line or the ground line and a part of the power supply line or the ground line.
Moreover, one first diffusion region (92) is provided for each block region. Therefore, even if noise enters the first diffusion region, only this block region is interfered with, and other block regions are hardly affected. for that reason,
It is effective as a measure for preventing mutual interference between blocks.

Further, since the protection diode can be formed on the outer periphery of the block area, the pattern arrangement in the block area is hardly affected and the layout can be arranged in an orderly manner.

Secondly, by providing an N-type dummy island (102) surrounded by an isolation region around the N-type second diffusion region (93), the second diffusion region (93) and the second diffusion region (93) are separated from each other. The parasitic thyristor operation due to the diffusion region (92) of No. 1 can be prevented. Therefore, it is possible to prevent the destruction caused by the operation of the parasitic thyristor. Here, the circuit element connected to the power supply line V _CC can be protected from being destroyed.

Thirdly, a power supply line on the first diffusion region (92),
Since the first electrode and the second electrode can be extended, the first diffusion region can be effectively utilized and the increase of the chip area can be prevented.

Fourth, when the upper surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size by the division line ( 5 ) and a plurality of electronic circuit blocks having different functions are accommodated in an integer number of mats, the electronic circuit block is formed. Each design can be done in parallel and the design period can be greatly shortened. Further, since the electronic circuit block is divided into a certain number of elements and the design for each mat can be performed, the parallel design for each mat can also be performed. Further, since circuit changes such as deletion, addition and correction can be designed for each electronic circuit block or each block, only the change for each block or each mat is sufficient, and the design change of the entire IC is not necessary. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, other mats can be used as they are, and the reliability can be improved very much by modifying only the mat to be changed when the circuit is changed thereafter.

Moreover, since the mat is divided, the lower layers of the third power supply line and the third ground line can be effectively used. The first diffusion region (92) is connected to the power supply line by connecting the power supply line between the pads (90) ... (90) and the block region in the upper half of the chip and the block region in the lower half of the chip. Since the first power supply line extends to the lower end, it is possible to easily connect without providing another power supply line. The following measures are taken to avoid mutual interference between electronic circuit blocks. That is, the first diffusion region is provided for each block region. This has the advantage that even if noise enters the first diffusion region of a block, it is separated for each block, so that noise does not enter other blocks. On the contrary, if the first diffusion region is provided separately for each pad, this effect is further improved, but the connection with the power supply line becomes very complicated. Therefore, if each block is provided, there is an advantage that the number of connections with the power supply line can be reduced and also interference with other blocks can be prevented.

Further, since the first diffusion region is formed so as to surround the area where the mats A to J and the mats K to T are formed, it is possible to prevent noise from entering around the chip.

[Brief description of drawings]

FIG. 1 is a top view for explaining a formation position of a protection diode in a semiconductor integrated circuit of the present invention, FIG. 2A is a partially enlarged view of the protection diode of FIG. 1, and FIG. 2B is a view of FIG. 2A. A-
FIG. 2C is a partial enlarged view of the protection diode of FIG. 1, FIG. 3 is a top view showing a semiconductor integrated circuit of the present invention, and FIG. 4A is a semiconductor integrated circuit of the present invention. 4B is a cross-sectional view taken along the line AA ′ in FIG. 4A, FIG. 5 is a top view showing an electrode pattern of the semiconductor integrated circuit of the present invention, and FIG. 6 is the present invention. FIG. 7A is a diagram illustrating an AM tuner block, FIG. 7B is a diagram illustrating an FM front end block and an FM-IF block, and FIG. 7C is a multi-circuit diagram. FIG. 8 is a diagram for explaining a plex decoder block, FIG. 8 is a top view of a conventional semiconductor integrated circuit, FIG. 9 is a sectional view between block b and block c in FIG. 8, and FIG. It is a circuit diagram shown. (1) …… Semiconductor chip, (2) …… Divided area, (3)
...... First area, (4) ...... Second area, ( 5 ) ...... Partition line, (35), (36), (37), (38) ...... Third power supply line, (41 ), (42), (43) …… Second ground line, (69), (70), (71) …… Second power line, (72), (73), (74) …… 3 ground line, (90) …… pad, (91) …… block area, (9
2) …… first diffusion region, (93) …… second diffusion region,
(94) ... third diffusion region, (96) ... first electrode,
(97) …… Second electrode, (102) …… Dummy island.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 27/04 A 8427-4M (56) References JP 62-293660 (JP, A) Special features Kai 61-292341 (JP, A) JP 59-84542 (JP, A) JP 58-39053 (JP, A) JP 48-15483 (JP, A) JP 59-124740 (JP JP, A)

Claims (3)

[Claims] 1. Positioned on a semiconductor layer of a semiconductor chip,
A plurality of linear electronic circuit blocks, each having a semiconductor element arrangement region (mat) formed in the semiconductor layer, which has a plurality of shapes of substantially the same size, and a function of which the circuit size is substantially different. In the semiconductor integrated circuit, the semiconductor element of the electronic circuit is formed in the arrangement area (mat), and all the semiconductor elements of the electronic circuit block classified by the function have the arrangement area (mat) as a unit. As a plurality of placement regions (mats) obtained by dividing the total number of semiconductor elements of this electronic circuit block, the plurality of placement regions (mats) provided substantially corresponding to the electronic circuit block region around the semiconductor chip are provided. A pad, a first conductivity type diffusion region integrally formed between the electronic circuit block region and the plurality of pads corresponding to the electronic circuit block region. An area, a second diffusion region of one conductivity type provided in a lower layer of the plurality of pads, a semiconductor region of an opposite conductivity type having a junction with the second diffusion region and connected to ground, A first region that corresponds to a plurality of pads and that connects a plurality of third regions of the opposite conductivity type formed in the first diffusion region and the second diffusion region and the third diffusion region, respectively. A semiconductor integrated circuit comprising: an electrode; a second electrode connecting the first electrode to the electronic circuit block; and a power supply line connected to the first diffusion region. 2. The semiconductor integrated circuit according to claim 1, wherein a dummy island region of one conductivity type surrounded by an isolation region is provided around the second diffusion region. 3. The semiconductor integrated circuit according to claim 1, wherein the power supply line is formed on the first diffusion region.