JPH0632041B2 - Depth information buffer control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention controls a depth information buffer (hereinafter referred to as a Z buffer) used for hidden surface removal in three-dimensional computer graphics. Regarding the device.

(Prior Art) When three-dimensional graphic processing is performed using a computer, when multiple objects overlap, which edge and which surface of which object are visible are determined, and as a result, only the visible surface is determined. Perform hidden surface removal for display. Conventionally, there are various hidden surface removal algorithms (Computer Graphics: JD FOLEY / A.
VAN DAM P. P. 565-585), among others, the Z-buffer algorithm is simple and widely used. In this Z-buffer algorithm, the Z value (depth value) for each pixel on the screen is stored in a memory called a Z buffer, and each point in the polygon (the coordinate on the screen is x,
(represented by y) is calculated, and this calculation result is compared with the Z value corresponding to the (x, y) point in the Z buffer, and if the former is smaller, the refresh buffer is written.
If not, writing is not performed.

Here, a configuration example of a processing system using a conventional Z buffer is shown in FIG. 3, and its operation timing is shown in FIG. In FIG. 3, I buffer (luminance information buffer)
Reference numeral 31 stores the I value (luminance value) of each point on the screen. Normally, a dual port (2 port) memory is used, and it is read out at high speed from the serial port side. This read signal is sequentially converted into a video signal and displayed on the image display device 32 such as a CRT display. Control LSI 33
Is the address (x, y) of each point of the object, I
(X, y) and Z (x, y) are calculated, the address is supplied to the I buffer 31 and the Z buffer 34 in common, and I
(X, y) is supplied to the I buffer 31, Z (x, y) is compared as described later, and as a result of the comparison, if writing is necessary, a new Z value is supplied to the Z buffer 34, and I The write control of the buffer 31 and the Z buffer 34 is performed. The processing by the control LSI 33 basically comprises four cycles. That is, in the first cycle, a point (xi _i , yi _i ) on the screen (i = 0, 1 ...)
Address, I, Z are calculated. In the second cycle,
The address is given to the Z buffer 34, and the above (xi, y
i) Read Z '(xi, yi) which is the Z value corresponding to the point. In the third cycle, the read Z ′ (xi,
yi) and the calculated Z value Z (xi, yi) are compared, and if Z '(xi, yi)> Z (xi, yi), Z (xi, yi) is closer to the front (depth). Is shallow), the I value and the Z value at the point (xi, yi) are correspondingly written in the I buffer 31 and the Z buffer 34 in the next fourth cycle.

However, in the above-described processing, one cycle is required to read the Z value, so that there is a problem that the processing speed is reduced accordingly.

(Problems to be Solved by the Invention) The present invention has been made to solve the problem that the processing speed decreases as the Z value is read as described above. An object of the present invention is to provide a depth information buffer control device capable of preventing a decrease.

EFFECTS OF THE INVENTION (Means for Solving Problems) A depth information buffer control device of the present invention has a random port and a serial port as depth information buffers for hidden surface removal in three-dimensional computer graphics. Using the port memory, the Z value is read from the serial port and input to the control integrated circuit for pipeline processing. As a result of the processing, the internally calculated Z value is used as the 2 port. It is characterized by writing from a random port of the memory.

(Operation) Reading and writing can be performed simultaneously on the 2-port memory, and it takes some setup time for serial input of the Z value to the control integrated circuit, but hidden surface removal at each point on the screen can be performed in substantially one cycle. , The processing speed is greatly improved.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

In the three-dimensional graphic processing apparatus shown in FIG. 1, reference numeral 1 denotes an I buffer (luminance information buffer) in which I values (luminance values) at respective points on the screen are stored, and normally a 2-port memory is used. A Z buffer (depth information buffer) 2 stores the Z value of each point on the screen, and is a memory having two ports, a random port and a serial port. It is desirable that the random port be capable of high-speed mode access (high-speed page access) because the filling processing on the screen in 3D graphics is performed in the horizontal direction of the screen and the memory access is performed in the same row (row). This is because the column is often accessed in sequence in (). A control LSI 3 includes a memory control unit that supplies various control signals to the buffers 1 and 2, and
Address (x, y) of each point of the object, I (x,
y) and Z (x, y) are calculated, an address is commonly supplied to the I buffer 1 and the Z buffer 2 via the register 4, and I (x, y) is randomized to the I buffer 1 via the register 5. It is supplied to the port and Z (x, y) is selected by the selector 12
Via the register 13 to one input of the comparator 13 for comparison with the other input which will be described later, and as a result of the comparison, the Z value internally calculated when it is necessary to write the value of the Z buffer 2 of the Z buffer 2 via the register 6. It has a function of supplying to the random port and supplying the write control signals of the I buffer 1 and the Z buffer 2 via the register 7. Further, the control LSI 3 is
The Z value read from the serial port of the Z buffer 2 is serially input and guided as the other input of the comparator 13 through the internal two-stage registers 8 and 9, and the pipeline arithmetic function is provided. Have. The selector 12 selects the Z value passed through the register 6 when comparing the first points, and selects the Z value after the calculation when comparing the second and subsequent points. Reference numeral 10 is a video signal conversion circuit that converts the I value read from the serial port of the I buffer 1 into a video signal and supplies the video signal to an image display device (for example, a CRT display) 11.

In the case of the 2-port memory, a so-called internal data transfer cycle is required to transfer data for one row from the memory cell array to the shift register for serial conversion in order to read from the serial port. After this transfer, data is sequentially read from the serial port while incrementing from the designated address in synchronization with the serial control clock.

Next, the operation of the above three-dimensional processing apparatus will be described with reference to the timing chart of FIG. Of the ▲ ▼ (row address strobe) signal and ▲ ▼ (column address strobe) signal supplied from the memory control unit of the LSI 3 to the buffers 1 and 2, when the ▲ ▼ signal becomes active (low level), the memory is If the ▲ ▼ / ▲ ▼ (data transfer control / output enable) signal output from the control unit is active (low level),
The serial output of the Z buffer 2 starts the operation of serially inputting to the LSI 3. That is, in the Z buffer 2, internal transfer occurs, and the ▲ ▼ / ▲ ▼ signals become inactive with the data of the address AO (actually including the row address and the column address) at this time as the head. After that, each time the column address is counted up in synchronization with the serial control clock SC output from the memory controller, the Z buffer 2 sequentially outputs the L address.
Input to SI3 sequentially. In the LSI 3, after serial input data is latched in the two-stage registers 8 and 9 at the trailing edge of the serial control clock SC, this data Z _H is compared with the Z value calculated internally, and Z _H is the above Z value. If it is larger than the value, the ▲ ▼ (write enable) signal is activated and the address A of the I buffer 1 and the Z buffer 2 is set.
I _OUT, which is the I value internally calculated in O and held in the register 5, and Z _OUT , in which the Z value is held in the register 6, are written in the next cycle. In this case, if Z _H is smaller than the Z value, writing is not performed.

Here, the operation during the serial input setup period shown in FIG. 2 will be further described. In addition, register 4,
5, 6, and 7 latch data at the falling edge of the clock CLOCK. However, the registers 4, 5, and 6 are held during the serial input setup period. The first point comparison is done in the cycle indicated by. Register 6 at this time
Is ₀ , and the selector 12 selects this value. Therefore, the comparator 13 compares Z ₀ and Z _H, and the result is latched in the register 7. The operation of I _OUT and Z _OUT is the same as that of address A, and I ₀ and Z _{0 in the} cycle respectively.
It has become. The comparison of the following points is performed in the cycle shown by, at which time the selector 12 selects the calculated Z value, that is, Z ₁ , and the comparator 13 selects the selected Z value and the value of Z _H , which is also Z ₁ . Compare. In the LSI 3, calculation of the internal address, I value, and Z value is stopped from the start of serial input to the end of the first comparison and writing. Then, after the first writing is completed, internal calculation is also started, and Z values are input one after another in a pipeline → comparison →
Writing is done. Therefore, it is a time required for setup from the start of the serial input to the output of write data.

The pipeline-like operation is broken when the read page of the Z buffer 2 is changed and the row address and the column address are reset, which requires several cycles. In the case of data (when accessing a full page, etc.), the time loss associated with the above resetting can be ignored, and it can be considered that processing is performed in the cycle of the basic clock of the LSI as a whole.

Here, the above embodiment and the conventional example will be compared. In the conventional example, the cycle time for reading a buffer (memory) and the cycle for processing (calculation, writing) inside the LSI are different (specifically, the memory cycle is L
It is considered to be about three times the basic cycle of SI), and when converted to the basic cycle of LSI, a total of 8 cycles are required. On the other hand, in the above embodiment, several cycles are required for the setup time of the serial input, but when the pipeline operation is started, the basic cycle is processed. Therefore, in the above-mentioned embodiment, the maximum is a little less than 8 times compared with the conventional example.
Normally, it is possible to operate at a speed 4 to 5 times.

[Effects of the Invention] As described above, according to the depth information buffer control device of the present invention, it is possible to prevent a decrease in the processing speed due to the reading of the Z value, and to perform the hidden surface removal in three-dimensional computer graphics at high speed. Can be processed in real time and the real-time property can be further improved.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of a depth information buffer control device of the present invention, FIG. 2 is a timing diagram showing an operation example of FIG. 1, and FIG. 3 is a conventional depth information buffer control device. FIG. 4 is a timing chart showing the operation example of FIG. 1 ... I buffer, 2 ... Z buffer, 3 ... L for control
SI.

Claims (1)

[Claims] 1. A depth information buffer controller used for removing a hidden surface from an object as graphic information in three-dimensional computer graphics, the controller having a random port and a serial port, the hidden surface from the object. A 2-port memory as a buffer for storing depth information for removing the depth information, a reading means for sequentially reading the depth information from the serial port of the 2-port memory in synchronization with a clock signal, and a reading means for reading the depth information. Holding means for holding the depth information for the period of the basic clock of the clock signal, calculation means for calculating the depth information of the object, depth information calculated by the calculation means, and depth information held by the holding means. A comparison hand that compares in synchronization with the basic clock And as a result of the comparison by the comparing means, if the held depth information is larger, the depth information calculated by the calculating means is written from the random port to the address designated by the reading means of the two-port memory. A depth information buffer control device, comprising: a writing unit.