JPH0642214B2 - Address translator - Google Patents

Description

DETAILED DESCRIPTION [Outline] A conversion index buffer (hereinafter, referred to as TL) having a plurality of entries.
B; Translation Lokaside Buffer), in an address translation device, an auxiliary TLB is provided, and an entry in which a failure is detected and an auxiliary T
The same address translation data is re-registered in the LB a predetermined number of times, and when all the registered data match, the entry is validated.

[Industrial application field]

The present invention relates to improvement of an address translation device in a virtual memory system.

In a virtual memory data processor, a TLB is used to convert a virtual address into a real address at high speed.

This TLB is an item (entry) for registering a plurality of sets of address conversion data composed of segment numbers and page numbers of virtual addresses and corresponding real page addresses.
Is composed of a high-speed buffer, and when the virtual address output by the processor is registered in this TLB, the real page address is output and the real address is generated together with the displacement within the page.

In the address translation device using the TLB, when a failure occurs in an entry, the entry is separated, but a single detection may not necessarily be a failure, and when a limited number of entries are separated. , T
There is a problem that the probability (hit rate) that the corresponding address translation data exists in the LB is lowered.

Therefore, there is a demand for an address translation device that solves the above problems and prevents the hit rate from decreasing.

[Conventional technology]

FIG. 3 shows a block diagram of a conventional address translation device.
In the figure, 1 is a TLB composed of a plurality of entries 2,
The segment number 50 and the page number 51 of the virtual address 53 output from the processor are respectively compared with the contents of the entry 2, and when they match, the real page address in the main memory 5 registered in the entry 2 (hereinafter referred to as page Address) 54 for outputting a failure and failure detection means for detecting a failure of each entry 2. Reference numeral 2 denotes an entry, a segment number 50 and a page number 51.
And a buffer for registering the page address 54, which is provided in a plurality of sets. Reference numeral 3 denotes a registration unit, which selects an entry 2 to be replaced and converts the address when the corresponding address does not exist in the TLB 1. Data is registered. Reference numeral 4 is a conversion table in which a page address 54 of the main memory 5 is associated with a virtual address, which is stored in the main memory 5.

In the address translation device having the above configuration, when the virtual address 53 is now output from the processor, the segment number 50 and the page number 51 are input to the TLB 1 and compared with each entry 2.

When this virtual address matches, the page address 54
Is output and added with the displacement 52 to generate a real address 56.

Here, if the corresponding virtual address does not exist in TLB1, the conversion table 4 is referred to generate a real address, and the virtual address and page address are registered in TLB1.

Here, when a failure is detected in the entry 2, the registration unit 3 disconnects the entry, and thereafter, registration in the entry is stopped.

[Problems to be solved by the invention]

As described above, when an entry failure is detected, the entry is separated, and the hit rate decreases.

However, the failure is detected by checking the registered data and may be a temporary failure detection.

Therefore, it is an object of the present invention to provide an address translation device that prevents entry separation due to temporary failure detection as described above and improves the reduction in hit rate.

[Means for solving problems]

In order to solve the above problems, the address translation device of the present invention includes an auxiliary translation index buffer (7) and an entry (2) in which a failure is detected, as shown in FIG. Registration means (21) for re-registering the same address translation data as the auxiliary translation index buffer (7) a predetermined number of times, and respective address translation data corresponding to the re-registered entry and the auxiliary translation index buffer. And a processing unit (20) for validating the entry when the comparison matches a predetermined number of times.

[Action]

When a failure of an entry is detected, invalid data is stored in the bit indicating valid / invalid of the entry, and the auxiliary TLB is stored.
At the same time, the entry is reregistered a predetermined number of times.

For each re-registration, the address translation data of the entry and the auxiliary TLB are compared, and when a mismatch occurs, the detachment notification bit provided for each entry is flagged and the entry is detached.

During this period, the page address is not output from the entry due to the invalid data.

For the entries that have been registered a predetermined number of times and have all matched, the valid data is stored in the valid / invalid bit and the entry is brought into the registered state.

As described above, the entry in which the failure is detected is re-registered a predetermined number of times, and when the entries are compared with the auxiliary TLB and all match, the entry is validated to prevent disconnection due to temporary failure detection.

〔Example〕

 An embodiment of the present invention will be described with reference to FIG.

FIG. 2 (a) shows a block diagram of the address translation device of the embodiment, and FIG. 2 (b) shows an operation flowchart.

In this embodiment, an area for storing a valid / invalid bit and a separation notification bit is provided for each TLB entry. In the figure, 6 is a valid / invalid bit 58 for each entry 2.
And a TLB to which the separation notification bit 59 is added, 7 is an auxiliary TLB provided with one or more sets of entries, and the address translation data is stored by the gate 8. 9 is a comparison unit, and the entry 2 and the auxiliary TLB 7 are provided. Comparing the registered page addresses 54, 10 is an opening / closing control unit that opens and closes the operations of the gate 8 and the comparing unit 9, and 14 is a registration unit having a conventional registration function. A registering means (21) and a processing means (2) for setting the valid / invalid bit 58 and the disconnection notification bit 59.
0), and 11 is a counter 1 for counting the set value 12 and the number of re-registrations.
3 is a comparator for notifying the switching control unit 10 when they match with each other, and 15 is a gate that is opened if the entry 2 is valid when the TLB 6 is referred to. It represents the same object.

FIG. 2 shows the re-registration operation of the registration unit 14 when a failure is detected in the entry 2 in the address translation device configured as described above.
An explanation will be given with reference to (b).

(1) When the fault detection signal 60 is output at the time of registration or address, invalid data is set in the valid / invalid bit 58 corresponding to the entry 2, and the gate 8 and the comparison unit 9 are operated to re-register. To do. (A, b) That is, the page address 54 corresponding to the output virtual address is read from the conversion table 4, and along with the virtual address, the entry 2 and the auxiliary TL in which the failure is detected are detected.
Re-register with B7.

(2) As a result, the page addresses 54 registered in the entry 2 and the auxiliary TLB 7 are compared by the comparison unit 9, and when they do not match, the disconnection notification bit 59 is flagged,
The re-registration operation ends. (F, G) (3) If they match, register again in the same entry 2 and repeat the operation in item (2). (D, b, c) (4) Whether or not the comparator 11 notifies the end of the predetermined number of times or the operations of the gate 8 and the comparator 9 are stopped and they are all in agreement, valid data is set in the valid / invalid bit 58. set. (E) As a result, the registered page address 54 is output from the entry 2 and is used for subsequent registration.

In the above operation, valid / invalid bit 5 during re-registration
By making 8 invalid, the gate 15 is closed and the page address 54 is not output from that entry.

Although the disconnection notification bit 59 is provided in the TLB 6, it may be provided in the registration unit 14 for management.

As described above, by providing the auxiliary TLB, and registering the same address translation data a predetermined number of times in the entry in which the failure is detected and comparing it, the failure detected temporarily can be checked, and the hit rate can be checked. Can be prevented.

〔The invention's effect〕

The present invention is to provide an address translation device which is provided with an auxiliary TLB, and when a failure is detected, re-registers the entry and the auxiliary TLB for comparison, and makes the entry valid when they match a predetermined number of times. Therefore, the effect of preventing the hit rate from decreasing is extremely large.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 (a) is a block diagram of an address translator of the embodiment, FIG. 2 (b) is an operation flowchart diagram, and FIG. 3 is a block diagram of a conventional address translator. Is.
In the figure, 1 is a conversion index buffer TLB, 2 is an entry, 3 is a registration unit, 4 is a conversion table, 5 is a main memory, 6 is a TLB of the embodiment, 7 is an auxiliary TLB, 8 is a gate, 9 is a comparison unit, Reference numeral 10 is an opening / closing control unit, 11 is a comparator, 12 is a set value, 13 is a counter, 14 is a registration unit, 15 is a gate, 20 is a processing unit, 21 is a registration unit, 50 is a segment number, 51 is a page number, 52. Is a displacement, 53 is a virtual address, 54 is a page address, 56 is a real address, 58 is a valid / invalid bit, 59 is a disconnection notification bit, and 60 is a failure notification signal.

Claims (1)

[Claims] 1. An address translation device having a translation index buffer comprising a plurality of entries (2) for registering address translation data, an auxiliary translation index buffer (7), and an entry (2) in which a fault is detected. Registration means (21) for re-registering the same address conversion data in the auxiliary conversion index buffer (7) a predetermined number of times, and corresponding address conversion of the re-registered entry and the auxiliary conversion index buffer. An address translation device comprising: a comparison unit (9) for comparing data; and a processing unit (20) for validating the entry when the comparison matches a predetermined number of times.