JPH0652898B2 - Subordinate clock switching control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a switching control circuit used in a digital synchronous transmission system including an active (N system) and a standby (E system), and particularly to an N system including frame position information. And a dependent clock switching control circuit for controlling switching of the E-system input clock.

(Prior Art) Generally, in a digital synchronous transmission system including an N system and an E system, the N phase and E system clocks of the same phase, to which various devices used in the digital synchronous transmission system are subordinate, may be switched as necessary. .

Conventionally, a switching control circuit of this type is known as shown in FIG.

These N-system and E-system clocks include frame position information such as a clock with a 64K + 8K-400Hz bipolar violation (hereinafter referred to as BV).

The conventional switching control circuit is a bi-bolor / unipolar converter 1, a selection circuit 2, an N system disconnection detector 3, an E system disconnection detector 4, B.
V detector 5, tank circuit 6, and frequency division counter (frequency division CT
R) 7, and the N-system and E-system disconnection detectors 3 and 4 operate the selection circuit 2 based on the disconnection information of the N-system input and the E-system input, respectively. The BV detector 5 detects the frame position information (302) from the clock selected by the selection circuit 2 and constantly loads (CTR cue) to the frequency division CTR7, and the frequency division C
The reference frame pulse in the device is generated from TR7.

(Problems to be Solved by the Invention) In the above-described conventional control circuit, it is determined that a disconnection occurs after an abnormality actually occurs in the input clock due to a technical limitation when implementing the clock input disconnection detection circuit. It takes a certain amount of time to judge. For this reason, the abnormal clock is selected during that time, and the frame position detection circuit (BV detection circuit) malfunctions, and the divided CTR is erroneously loaded for a moment. As a result, the reference frame pulse in the device generated from the CTR output has a phase jump, which may cause not only a data error but also various alarms inside the device.

(Means for Solving the Problems) According to the present invention, it is used in a digital synchronous transmission system including N-system and E-system devices, and inputs N- and E-system clock inputs for slaves having the same phase and having frame position information. In a switching control circuit for switching, selecting means for selecting one of the N-system clock and E-system clock, input disconnection detection means for detecting N-system and E-system clock input disconnection respectively, and detecting the frame position information. A frame position detecting means for generating a position detecting pulse, a changing point generating means for generating a trigger pulse indicating a selective changing point between the N system and the E system by the output of the input disconnection detecting means, and based on the trigger pulse Timing generating means for generating a timing pulse at a predetermined timing, and a load pulse generator based on the position detection pulse and the timing pulse. A load control means for generating a reference frame pulse, and a frequency division counter means for generating a reference frame pulse driven based on the load control means, when the power is turned on or when the N system and the E system are switched. In addition, the load control means drives the frequency division counter means based on the position detection pulse and the timing pulse, and in other cases, the self-feedback load is applied by the frequency division counter means. A subordinate clock switching control circuit is obtained.

(Examples) Next, the present invention will be described by examples. Referring to FIG. 1, this switching control circuit has a frame position information (110) and a clock (tank) detected by the BV detector 5 when the N system input (101) is selected by the selection circuit 2 when the power is turned on. It is assumed that the circuit 6 is operating normally by the clock (100) beaten by the circuit 6.

Here, also referring to FIG. 2, an abnormality occurs in the N-system input 101, a disconnection is detected by the N-system disconnection detector 3, and the N-system disconnection detection signal 103 is transmitted from the N-system disconnection detector 3. To be done. The selection signal 105 changes according to the N-system input disconnection detection signal 103,
As a result, the selection circuit 2 switches from N-system selection to E-system selection. On the other hand, the change point generation circuit 8 generates a trigger pulse 106 according to the change of the selection signal 105, and the trigger pulse 106 is input to the timing generation circuit 9. Timing circuit 90 is triggered by the rising trigger of trigger pulse 106 immediately after switching from N system to E system.
Unstable frame position pulse 110 detected by V detector 5
Thus, the timing pulse 107 is generated with a timing of Δt ₁ time so that the divided CTR7 is not loaded. The timing circuit 9b is driven by the rising trigger of the timing pulse 107, and generates the pulse 108 having a time width of Δt ₂ . Then, the timing generation circuit 9 generates the pulse 109 only during this Δt ₂ . This pulse 109 is input to the load control circuit 10, where a reload pulse 111 is generated. As a result, the frequency division CTR 8 can be loaded by the frame position pulse 110. A load pulse 112 due to self-feedback is applied to this frequency-divided CTR7 at the same cycle as that of the frame position 110.
When the load is applied by, the Δt ₂ time elapses, and even after the reload pulse 111 is no longer loaded, the self-feedback load pulse 112 continues the normal operation in the same cycle.

Here, the time Δt ₂ is the frame position pulse at least once.
The time required for loading by 110 is set, and the time Δt ₁ is set at least as long as the unstable state immediately after N → E or E → N switching can be cleared.

In this way, this circuit constantly monitors the N system input and the E system input, and when the active system is disconnected, that is, N → E or E → N.
When the switch is switched to, and only when the power is turned on, the predetermined timing is set, the divided CTR is once loaded with the frame position detected from the input clock, and then the self-feedback operation continues.

(Effect of the Invention) As described above, according to the present invention, when the power is turned on or N
Only when the system → E system, E system → N system is switched, a predetermined timing is taken, and the divided CTR is loaded once by the frame position information detected from the input clock, and at other times. Is configured to apply self-feedback load by the divided CTR itself, so when the active system clock is abnormal, that is, N
When the subordinates are switched from system to E system or from E system to N system, phase skipping does not occur in the reference frame pulse in the device, and data error and other alarms do not occur. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a switching control circuit according to the present invention, FIG. 2 is a timing diagram for explaining the operation of the switching circuit shown in FIG. 1, and FIG. 3 is a conventional switching control circuit. It is a block diagram shown. 1 ... B / U converter, 2 ... selection circuit, 3 ... N system disconnection detector, 4 ... E system disconnection detector, 5 ... BV detector, 6 ... tank circuit, 7 ... minute Zhou CTR, 8 ... Change point generation circuit, 9
...... Timing generator circuit, 10 …… Load control circuit, 100
…… Tank circuit output tank, 101 …… N system clock input, 102 …… E system clock input, 103 …… N system input disconnection signal, 104 …… E system input disconnection signal, 105 …… N / E system selection signal ， 1
06 …… NE system / change point trigger pulse, 107 …… Trigger pulse after timing, 108 …… Mask pulse for external load, 109 …… Mask pulse for external load (after retiming), 110 …… Frame position by external input Pulse, 111
...... CTR load pulse by external input, 112 …… CTR load pulse by self-feedback, 113 …… CTR load pulse.

Claims (1)

[Claims] 1. A switching control circuit for use in a digital synchronous transmission system comprising N-system and E-system devices, for switching inputs of slave N- and E-system clock inputs of the same phase having frame position information. Selecting means for selecting either one of the E and E system clocks, an input disconnection detecting means for detecting an N system and E system clock input disconnection respectively, and a frame position detection for detecting the frame position information and generating a position detection pulse. Means, a change point generating means for generating a trigger pulse indicating a selected change point of the N system and the E system by the output of the input disconnection detecting means, and a timing pulse at a predetermined timing based on the trigger pulse. Timing generating means for generating a load pulse, load control means for generating a load pulse based on the position detection pulse and the timing pulse, and And a frequency division counter means for generating a reference frame pulse, which is driven based on the drive control means, and when the power is turned on or the N system and the E system are switched over, the load control means performs the position detection pulse. And a dependent clock switching control circuit, wherein the frequency dividing counter means is driven based on a timing pulse, and in other cases, a self-feedback load is applied by the frequency dividing counter means.