JPH0654884B2 - Transversal filter control circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an automatic waveform equalizer using a transversal filter and a transversal filter control circuit for a cross polarization interference canceller.

(Prior Art) Conventionally, a waveform equalizer using a transversal filter,
Regarding the cross polarization interference canceller, the transversal filter control circuit for controlling the tap weight circuit has a ninth
As shown in the figure, the ZF (Zero-Forcing) method was mainly used. As shown in FIG. 10, 2 ² = 4 as the received signal
Taking a value signal as an example, the signal of the path 1 (identification signal) indicating the polarity of the signal and the signal of the path 3 (error signal) indicating the direction of the intersymbol interference are obtained from the identification circuit and passed through the clock cycle delay circuit. In the ZF method, the product of the identification signal and the error signal is taken in different periods, and the output is integrated by the required number of bits to determine the tap weighting coefficient. However, the ZF method has a drawback that the control convergence is poor when the intersymbol interference is large, and the control pull-in range is narrowed and the characteristics of the entire apparatus are deteriorated once the control is brought into an asynchronous state. This defect is often mainly due to an error in the error signal. Note that the signal in the shaded area B in Fig. 10 always has a positive error, and the signal in the shaded area B always has a negative error. The maximum level error polarity method (MLE method) using has been invented, and the use of this MLE method makes it possible to eliminate the above-mentioned drawbacks. The MLE method performs a multiplication operation of an identification signal and an error signal by a normal ZF algorithm,
The error information is adopted only at the time point corresponding to the error information of the maximum level error area, and the error information in the previous maximum level error area is held in the other error areas.
Therefore, since the MLE method is adopted when the intersymbol interference amount at the time of synchronization pull-in or the synchronization holding is large, and the ZF method is adopted when the intersymbol interference amount at the time of synchronization holding is small, a transversal with a good synchronization pull-in characteristic is adopted. Although a filter control circuit can be realized, it has a drawback that the response of control is not improved.

(Problems to be Solved by the Invention) An object of the present invention is to provide a transversal filter control circuit which is excellent in synchronization pull-in characteristics and response characteristics and which is composed of all digital circuits.

(Means for Solving Problems) The present invention discriminates a demodulated signal with an A / D converter having sufficient accuracy, and ZF method or MZF method and MLE method are applied to a product of the discriminated signal and an error signal. The main features are that it has a switching function of both control algorithms and a shift bit select (SBS) function that automatically switches the number of stages of the reversible counter that integrates the multiplication output according to the magnitude of the intersymbol interference amount. . ZF method or MZ
It differs from the conventional one in that it has both the functions of the F method and the MLE method, and also has the SBS function of detecting the intersymbol interference amount and making the integration time constant variable.

(Example) First, Claim 2 will be described.

FIG. 1 is a schematic diagram of the first embodiment of the present invention, in which 24 is a demodulation signal input terminal, 25 is a clock input terminal, 26 is a 5-bit precision A / D converter, and 27 to 32 are delay circuits. , 33 and 34 are weighting circuits (connections for C _{-2 to} C ₂ tap output and weighting circuits are omitted), and path 1 and path 2 and path 1 to path 5
3 shows a path through which the information of (1) is input to the weighting circuit.

FIG. 2 is a principle diagram for explaining the first embodiment of the present invention and shows a control circuit for one tap. 35 is an exclusive OR circuit that takes the product of path 1 (identification signal) and path 3 (error signal), 36 is a maximum level error determination circuit that determines the maximum level error, and 37 is a path 3, path 4, path 5 For example, an asynchronous detection circuit that detects asynchronousness using error information sends "1" information when synchronous and "0" information when asynchronous. Reference numeral 38 is a hold having a clock stop function for sending the output of the multiplication result to the reversible counter, holding the clock, or driving the reversible counter with a clock controlled by the maximum level error determination circuit 36 and the asynchronous detection circuit 37 by using the output of the multiplication operation as an input. A circuit 39 receives the identification information (path 1, path 2) of the output of the A / D converter 25 and the error information (path 3, path 4, path 5) as an input, and when the error is large, sets the integration time of the multiplication result output. A circuit having a shift bit (SBS) function that automatically adjusts the position of the input digit of the reversible counter to control the integration time constant so as to shorten the integration time and lengthen the integration time of the multiplication result output in the steady state , 40
Is a reversible counter and is used as a digital integrating circuit.
The number of stages is controlled by the SBS control circuit.

FIG. 3 is a block diagram of the asynchronous detection circuit 37, in which the path 3 representing the direction of signal point deviation, that is, the direction of intersymbol interference, and the paths 4 and 5 representing the absolute amounts thereof are input, and the inverting OR circuit 4
6, the logical product circuit 47 and their outputs are passed as inputs to the logical sum circuit 48, and when the output is "1", the intersymbol interference amount becomes large. On the other hand, when the output is “0”, it can be determined that the intersymbol interference amount is small. The output signal is counter 49
When the output = “1” is present in two or more time slots out of 2 ⁴ = 16 time slots, it is judged as an asynchronous state and “0” is output to the output terminal 63. Details are described in Japanese Patent Application No. 60-38925.

FIG. 4 is a block diagram of the SBS control circuit 39. (a) is a control terminal CT using the error information path 3, path 4 and path 5.
The control information is output to 1 to CT4. (b) outputs the control information to the control terminal CT5 using the identification information path 1 and the path 2. Here, as a reversible counter, from 16 stages to 20
Consider a variable number of stages. Table 1 shows a reversible counter corresponding to the outputs of control terminals CT1 to CT5.
An example of setting the number of stages of 40 is shown.

For example, when "pass 3, pass 4, pass 5" is "111" and "pass 1, pass 2" is "11", CT1 = "0", C
T2 = "0", CT3 = "0", CT4 = "1", CT
5 = “0” and the number of stages of the counter is set to 16.

FIG. 5 shows a block diagram of the reversible counter 40. When the control information of the SBS control circuit is input to the T input terminals 73 to 77 and the intersymbol interference is the smallest, that is, the reversible counter has 20 stages, and the information of "1" is input to the input terminals 73 to 77. −
Flip-flops work from 79. At this time, the integration time becomes sufficiently long, and highly accurate correlation detection becomes possible. On the contrary, when the inter-code interference is the largest, that is, the number of stages of the reversible counter is 16, the information of "00001" is input to the input terminals 73 to 77, and the T-flip-flop operates from 83. At this time, the integration time becomes the shortest and the response speed becomes the fastest. 78
Tap weight with K-bit precision by inputting "up" or "down" control signal to the terminal and arbitrarily extracting K bits from the uppermost stage of the counter according to the required precision of the tap weight control signal. A control signal can be obtained. The control circuit for generating a K-bit control signal for one tap has been described above.
Alternatively, it is obvious that N number of the above-mentioned circuits are required because the multiplication operation of the error signal and the identification signal is performed at the time when they differ by an integer multiple. Also, the asynchronous detection circuit of FIG.
It is also possible to prepare one in the overall configuration diagram and distribute the control signal to each tap.

In the above description, the case of using the same signal for the identification information and the error information has been described. That is, this is an example of a transversal filter control circuit for a linear equalizer.

Next, claim 3 will be described. In general, the identification information and the error information may be different signals from each other. For example, in the orthogonal polarization (main polarization signal, different polarization signal) sharing,
By applying the present invention to the identification information and error information of the main polarization signal and the identification information of the different polarization signal, a control circuit of the cross polarization interference canceller can be configured.

FIG. 6 is a principle diagram for explaining the second embodiment of the present invention, in which a cross polarization interference canceller is constructed using a transversal filter control circuit, and 109 is a demodulator for main polarization. , 110 are demodulators on the side of different polarization, 111 and 112 are A /
When the cross-polarization interference from the different polarization side to the main polarization side is removed by the D converter, the output of the A / D converter 112 is input to the transversal filter 114 and the control information of the different polarization side is input. The identification information (path 1 ', path 2') is input to the control circuit 115. Main polarization side identification information (path 1, path 2) and error information (path 3, path 4,) from the output of the subtractor 116 that subtracts the output of the main polarization side discriminator 111 and the output of the transversal filter 114. The path 5) is detected and input to the control circuit 115.

FIG. 7 is a block diagram of the control circuit 115, in which the error signal path 3 on the main polarization side and the identification signal path 1'on the different polarization side are multiplied and input to the reversible counter. The signals input to the SBS control circuit are the error information path 3 on the main polarization side, the path 4 and the path 5 and the identification information paths 1'and 2'on the different polarization side. Similar to the equalizer.

FIG. 8 shows an example of the effect obtained when this control circuit is used.
In the cross-polarization interference compensator of FIG. 5, when given constant cross-polarization interference and controlled by the conventional ZF method,
The tap coefficient convergence time is 600 ms. On the other hand, when the circuit based on the principle of the present invention is used, the convergence time is 150 ms, and the control is converged at about 4 times the speed, so that the response speed can be increased and the effectiveness of the present invention has been confirmed. .

(Effects of the Invention) As described above, the present transversal filter control circuit has a function of automatically selecting both control of the MLE method and the ZF method or the MLE method and the MZF method, and integrates the multiplier output signal. For the reversible counter for this purpose, the number of stages of the reversible counter is varied based on the identification information and the error information. When the amount of error is large, the integration time is shortened and the response speed is increased. On the other hand, as we approach the steady state, we increase the integration time,
Stabilize the control. Moreover, by using the MLE method and the ZF method or the MLE method and the MZF method in combination, it is possible to provide a transversal filter control circuit capable of expanding the control pull-in range.

Although the embodiments of the present invention have been described for a normal transversal filter that uses a delay circuit having a delay amount T corresponding to a clock cycle, the delay amount is not limited to T,
It is obvious that the present invention can be applied to a transversal filter that uses a fractional space composed of delay circuits having a fraction T / n (n: natural number) of T.

[Brief description of drawings]

FIG. 1 is a block diagram of a transversal filter control circuit (7 taps) according to the present invention, FIG. 2 is an embodiment of the control circuit of the present invention (corresponding to 1 tap), FIG. 3 is a block diagram of an asynchronous detection circuit, and FIG. FIG. 6 is a block diagram of an SBS control circuit, FIG. 5 is a block diagram of a reversible counter, FIG. 6 is an embodiment in which the present invention is applied to a cross polarization interference canceller, and FIG. 7 is a cross polarization interference canceler. FIG. 8 shows an embodiment of the control circuit of the present invention when applied to the above, FIG. 8 is a diagram showing a measurement result showing the effect of the present invention, and FIG. 9 is a transversal filter control circuit by the conventional ZF method (7-tap configuration). FIG. 10 is a diagram showing an input / output relationship when a four-valued amplitude signal is identified. 1 ... Demodulation signal input terminal, 2 ... Clock input terminal, 3 ... A / D converter, 4-9 ... Delay circuit, 10-16 ... Exclusive OR circuit, 17-23 ... Integration circuit , 24 …… demodulation signal input terminal, 25 …… clock input terminal, 26 …… A / D converter, 27 to 32 …… delay circuit, 33, 34 …… tap weighting circuit, 35 …… exclusive OR circuit , 36 ...... Maximum level error judgment circuit, 37 ...... Asynchronous detection circuit, 38 ...... Hold circuit, 39 ...... SBS control circuit, 40 ...... Reversible counter, 41, 45 …… AND circuit, 42, 43 …… Inverting logical sum circuit, 44 ... Logical sum circuit, 46 ... Inverting logical sum circuit, 47 ... Logical product circuit, 48 ... Logical sum circuit, 49 to 56 ... T-flip-flop, 57 ... Clock signal input Terminals, 58 ... Multi-input AND circuit, 59 ... Multi-input OR circuit, 60 ... Hold circuit, 61 ... Delay gate circuit, 62 ... Inversion circuit 63 …… output terminal, 64,65,71 …… exclusive OR circuit, 66 …… AND circuit, 67 to 70,72 …… OR circuit, 73 to 77 …… control signal input terminal, 78 …… "Up" and "down" control signal input terminals, 79 to 85 ... T-flip-flop, 86 ... Inversion circuit, 87-104 ... NAND circuit, 105-108 ... OR circuit, 109 ... Main polarization side demodulator, 110 …… Different polarization side demodulator, 111, 112 …… A / D converter, 114 …… Transversal filter, 115 …… Control circuit, 116 …… Subtractor, 117 …… Main polarization Wave-side demodulation signal input terminal, 118 ... Hetero-polarization side demodulation signal input terminal, 119 ... Main polarization-side recovered clock input terminal, 120 ... Exclusive OR circuit, 121 ... SBS control circuit.

Claims (3)

[Claims] 1. In a digital communication system, an A / D converter 1 for identifying a received digital signal 1, an A / D converter 2 for identifying another received digital signal 2, and the A / D converter A multiplier for multiplying the polarity signal of the error obtained from the estimated value of the transmission data among the outputs of the D converter 1 and the identification polarity signal obtained from the output of the A / D converter 2, and the A / D converter Maximum level error determination circuit for determining the maximum level error region from the output of 1; an asynchronous detection circuit for estimating the synchronous / asynchronous state of the digital signal 1; a hold circuit using the output of the multiplier as an input signal; A digital integrator having an output as an input signal, and the digitizer according to the magnitude of the identification signal and the error signal of the output of the A / D converter 1 and the magnitude of the identification signal of the output of the A / D converter 2. And a circuit for varying the integration time constant of the integrator. In the asynchronous state, the hold circuit output is driven (conducted only at a time corresponding to the error information in the maximum level error region of the maximum level error determination circuit output). ), The previous state is held in other error areas, and in the case of a synchronous state, the hold circuit is controlled to drive for all error areas, and the error obtained from the output of the A / D converter 1 When the magnitude of the signal and the discrimination signal obtained from the output of the A / D converter 2 is large, the integration time constant of the integrator is reduced, and conversely, when the magnitude of the error signal and the discrimination signal is small, the integration time is reduced. A transversal filter control circuit, wherein a constant is increased and upper K bits of the integrator output are used as an output signal. 2. An A / D converter (26) having a multi-valued signal of 2 ^J (J: natural number) value as an input signal and having an output of (J + 2) bits or more, and an upper M of the A / D converter. _{For 1} (M ₁ > J) bits, a delay circuit 1 (30, 31, 32) having a delay tap that is an integral multiple of the clock cycle T, and a clock cycle T for the upper J bits of the A / D converter
Delay circuit 2 (27,28,2
9), and the delay circuit 2 that differs from the output of each delay tap for the (J + 1) th bit of the delay circuit 1 by an integer multiple of T
N multipliers (35) for multiplying the most significant bit of each delay tap output with each other, and the upper (J + 1) th bit or less of the A / D converter output,
An asynchronous detection circuit (37) for monitoring the synchronous / asynchronous state of the system using M ₂ (M ₂ : natural number) bits and the system clock signal as input signals, and each delay tap output for the upper (J + 1) bits of the delay circuit 1 N maximum level error judging circuits (36) for judging the maximum level error (MLE) as an input signal, and N for outputting each output to the N multipliers as an input signal.
A number of hold circuits (38), a determination circuit (44) for receiving the outputs of the asynchronous detection circuit and the outputs of the maximum level error determination circuits for controlling the hold circuits, and a high order (J + 1) of the delay circuit 1 ) Each delay tap output for the M ₁ bit or less and the upper J of the delay circuit 2
N shift bit select control circuits (39) each having a delay tap output for a bit as an input signal, and each shift bit select control circuit output as an input signal to determine the position of an input digit. It is equipped with a variable N L-stage reversible counter (40),
An N-tap transversal filter control circuit, which outputs upper K (K <L) bits of the L-stage reversible counter as a tap weight control signal. 3. A having a multi-valued signal of 2 ^J1 (J ₁ : natural number) value as an input signal and having an output of (J ₁ +2) bits or more
/ D converter 1 (111) and multi-valued signal of 2 ^J2 (J ₂ : natural number) values as input signals,
A / D converter 2 (112) having an output of J ₂ bits or more
A delay circuit 1 having a delay tap output that is an integral multiple of a clock period T for the upper M ₁ (M ₁ > J ₁ ) bits of the A / D converter 1, and the upper J _{2 of the} A / D converter _2. A delay circuit 2 having a delay tap output that is an integral multiple of the clock cycle T for bits,
N number of multiplications for multiplying each delay tap output for the (J ₁ +1) th bit of the delay circuit 1 and each delay tap output for the most significant bit of the delay circuit 2 that relatively differs by an integer multiple of T An A / D converter 1, an asynchronous detection circuit for monitoring the synchronous / asynchronous state of the system with M ₂ bits below the upper (J ₁ +1) th bit of the output of the A / D converter 1 and a system clock signal as input signals, and the delay circuit 1 The maximum level error (MLE) with each delay tap output for the upper (J ₁ +1) bits of
N maximum level error determination circuits for determining the above, and N for each output as an input signal to the N multipliers.
Hold circuits, a determination circuit for controlling the hold circuits, the determination circuit having the asynchronous detection circuit output and the maximum level error determination circuit output as inputs, and each delay tap output for the upper J ₂ bits of the delay circuit 2. And N shift bit select control circuits each having an input signal from each delay tap output for M ₃ (M ₃ : natural number) bits below the upper (J ₁ +1) th bit of the delay circuit 1, and each of the hold circuits. An L number of L-stage reversible counters whose output is an input signal and whose input digit position can be changed by the output of each shift bit select control circuit, and high-order K (K <L) bits of the L-stage reversible counters Is output as a tap weight control signal, an N tap transversal filter control circuit.