JPH0666416B2 - Electrostatic protection circuit - Google Patents
Electrostatic protection circuitInfo
- Publication number
- JPH0666416B2 JPH0666416B2 JP61175003A JP17500386A JPH0666416B2 JP H0666416 B2 JPH0666416 B2 JP H0666416B2 JP 61175003 A JP61175003 A JP 61175003A JP 17500386 A JP17500386 A JP 17500386A JP H0666416 B2 JPH0666416 B2 JP H0666416B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- electrostatic protection
- transistor
- protection circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
Landscapes
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、外部回路に接続される入出力端子を有し、２
つ以上の定電圧電源で駆動される半導体集積回路の静電
保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention has an input / output terminal connected to an external circuit,
The present invention relates to an electrostatic protection circuit for a semiconductor integrated circuit driven by one or more constant voltage power supplies.
第３図はこの種の半導体集積回路の従来例の回路図であ
る。FIG. 3 is a circuit diagram of a conventional example of this type of semiconductor integrated circuit.
この半導体集積回路は、内部回路９と、入出力端子１
と、内部回路９と正の定電圧電源４、地気、負の定電圧
電源５をそれぞれ接続する正電源端子６、接地端子７、
負電源端子８を有しており、さらにベース・エミッタ間
が抵抗で接続され、エミッタが負電源端子８に、コレク
タが入出力端子１にそれぞれ接続されたトランジスタ２
が静電保護回路として設けられている。トランジスタ２
と抵抗３により入出力端子１を最低電位にクランプする
ことにより、内部回路９を静電気から保護している。This semiconductor integrated circuit includes an internal circuit 9 and an input / output terminal 1.
And a positive power supply terminal 6 for connecting the internal circuit 9 and the positive constant voltage power supply 4, ground, and a negative constant voltage power supply 5, respectively, a ground terminal 7,
A transistor 2 having a negative power supply terminal 8, a base and an emitter connected by a resistor, an emitter connected to the negative power supply terminal 8 and a collector connected to the input / output terminal 1.
Is provided as an electrostatic protection circuit. Transistor 2
The internal circuit 9 is protected from static electricity by clamping the input / output terminal 1 to the lowest potential by the resistor 3 and the resistor 3.
上述した従来の静電保護回路は、｛（入出力端子１の電
圧）−（定電圧源５の電圧）｝＜（トランジスタ２のコ
レクタ・エミッタ間降伏電圧BVCER）が成立する場合に
しか使えず、一方、最近の半導体集積回路の高速化、広
帯域化の要求により接合が浅くなり、トランジスタのサ
イズが小さくなり、降伏電圧BVCERが小さくなっきてお
り、（１）式が満足できないために、第３図の静電保護
回路を実現できないことも起ってくる。The conventional electrostatic protection circuit described above can be used only when {(voltage of input / output terminal 1)-(voltage of constant voltage source 5)} <(collector-emitter breakdown voltage BV CER of transistor 2) holds. On the other hand, due to the recent demand for higher speed and wider bandwidth of semiconductor integrated circuits, the junction becomes shallower, the transistor size becomes smaller, and the breakdown voltage BV CER becomes smaller. It may happen that the electrostatic protection circuit shown in FIG. 3 cannot be realized.
本発明の静電保護回路は、入出力端子にコレクタが接続
され、最低電位以外の定電圧電源にエミッタが接続され
たトランジスタと、該トランジスタのベースに一端が接
続され、エミッタに他端が接続された抵抗を有する。The electrostatic protection circuit of the present invention has a transistor whose collector is connected to an input / output terminal and whose emitter is connected to a constant-voltage power supply other than the lowest potential, and one end of which is connected to the base of the transistor and whose other end is connected to the emitter. Have resistance.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の静電保護回路の一実施例を有する半導
体集積回路の回路図である。第２図中と同番号は同じも
のを示している。FIG. 1 is a circuit diagram of a semiconductor integrated circuit having an embodiment of the electrostatic protection circuit of the present invention. The same numbers as in FIG. 2 indicate the same things.
本実施例の静電保護回路は、入出力端子１にコレクタが
接地端子７にエミッタが接続された、つまり接地された
トランジスタ２と、トランジスタ２のベースに一端が接
続され、エミッタに他端が接続された抵抗３で構成され
ている。In the electrostatic protection circuit of this embodiment, one end is connected to the base of the transistor 2 and the transistor 2 in which the collector is connected to the input / output terminal 1 and the emitter is connected to the ground terminal 7, that is, the other end is connected to the emitter. It is composed of a connected resistor 3.
入出力端子１の電圧V1は、トランジスタ２のエミッタが
接続されている定電圧源の電圧、本実施例の場合、（ト
ランジスタ２のコレクタ・エミッタ間降伏電圧BVCER）
＜｛（入出力端子１の電圧V1）−（定電圧源５の電
圧）｝であっても、V1＜（トランジスタ２のコレクタ・
エミッタ間降伏電圧BVCER）が満足されれば、本実施例
の回路は静電保護の働きをする。The voltage V 1 of the input / output terminal 1 is the voltage of the constant voltage source to which the emitter of the transistor 2 is connected, and in the case of this embodiment (the collector-emitter breakdown voltage BV CER of the transistor 2)
<{(Voltage of input / output terminal 1 V 1 )-(voltage of constant voltage source 5)}, V 1 <(collector of transistor 2
If the emitter-to-emitter breakdown voltage BV CER ) is satisfied, the circuit of this embodiment functions as an electrostatic protection.
第２図は第１図の半導体集積回路の断面図である。Ｐ型
基板14の上にトランジスタ２のコレクタＮ領域15が形成
され、この中に入出力端子１と接続されたコレクタコン
タクト用高濃度Ｎ領域10が形成されている。コレクタＮ
領域15に抵抗３、トランジスタ２のベース領域13が設け
られ、この中に、エミッタ用高濃度Ｎ領域12、ベースコ
ンタクト用高濃度Ｐ領域11が形成されている。上記の構
造からコレクタＮ領域15とＰ型基板14はダイオードを形
成している。入出力端子１に印加される静電圧はトラン
ジスタ２のコレクタ・エミッタ間降伏電圧BVCERによっ
てクランプされる。入出力端子１に印加される最低電位
より低い電圧は、前記ダイオードにより最低電位にクラ
ンプされる。したがって、本実施例の静電保護回路は、
半導体集積回路の内部回路を正負の静電気から保護す
る。FIG. 2 is a sectional view of the semiconductor integrated circuit of FIG. A collector N region 15 of the transistor 2 is formed on a P-type substrate 14, and a collector contact high concentration N region 10 connected to the input / output terminal 1 is formed therein. Collector N
A resistor 3 and a base region 13 of the transistor 2 are provided in the region 15, and an emitter high-concentration N region 12 and a base contact high-concentration P region 11 are formed therein. From the above structure, the collector N region 15 and the P-type substrate 14 form a diode. The static voltage applied to the input / output terminal 1 is clamped by the collector-emitter breakdown voltage BV CER of the transistor 2. A voltage lower than the lowest potential applied to the input / output terminal 1 is clamped to the lowest potential by the diode. Therefore, the electrostatic protection circuit of this embodiment is
Protects internal circuits of semiconductor integrated circuits from positive and negative static electricity.
以上説明したように本発明は、多電源駆動の半導体集積
回路の入力端子にそのコレクタが接続され、そのエミッ
タが最低電位以外の定電圧源に接続されたトランジスタ
と、そのトランジスタのベースとエミッタの間に接続さ
れた抵抗により、低いコレクタ・エミッタ間降伏電圧を
持つトランジスタを使用しても、静電保護回路を実現す
ることができる効果がある。As described above, the present invention provides a transistor whose collector is connected to the input terminal of a semiconductor integrated circuit driven by multiple power supplies and whose emitter is connected to a constant voltage source other than the lowest potential, and the base and emitter of the transistor. Even if a transistor having a low collector-emitter breakdown voltage is used, the electrostatic protection circuit can be realized by the resistor connected between them.
第１図は、本発明の静電源保護回路の実施例を有する半
導体集積回路の回路図、第２図は第１図の実施例の断面
図、第３図は従来例の静電保護回路を有する半導体集積
回路の回路図である。 １……半導体集積回路の入出力端子、 ２……静電保護回路のトランジスタ、 ３……静電保護回路の抵抗、 ４……正の定電圧源、 ５……負の定電圧源、 ６……正電源端子、 ７……接地端子、 ８……負電源端子、 ９……半導体集積回路の内部回路。FIG. 1 is a circuit diagram of a semiconductor integrated circuit having an embodiment of a static power supply protection circuit of the present invention, FIG. 2 is a sectional view of the embodiment of FIG. 1, and FIG. 3 is an electrostatic protection circuit of a conventional example. FIG. 3 is a circuit diagram of a semiconductor integrated circuit included therein. 1 ... I / O terminal of semiconductor integrated circuit, 2 ... Electrostatic protection circuit transistor, 3 ... Electrostatic protection circuit resistance, 4 ... Positive constant voltage source, 5 ... Negative constant voltage source, 6 ...... Positive power supply terminal, 7 ... Grounding terminal, 8 ... Negative power supply terminal, 9 ... Internal circuit of semiconductor integrated circuit.
Claims (1)
前記第１の電圧とは異なる第２の電圧が供給される第２
の電源端子とを有する内部回路に接続された入出力端子
と、前記入出力端子にコレクタが接続されベースが抵抗
を介してエミッタに接続されエミッタが前記第２の電源
端子に接続されたトランジスタと、前記第１及び第２の
電圧の何れとも異なる第３の電圧が供給される第３の電
源端子と、前記入出力端子と前記第３の電源端子との間
に接続されたダイオードとを備えた静電保護回路。1. A first power supply terminal supplied with a first voltage and a second power supply terminal supplied with a second voltage different from the first voltage.
An input / output terminal connected to an internal circuit having a power supply terminal, and a transistor having a collector connected to the input / output terminal, a base connected to an emitter through a resistor, and an emitter connected to the second power supply terminal. A third power supply terminal to which a third voltage different from the first and second voltages is supplied, and a diode connected between the input / output terminal and the third power supply terminal. Electrostatic protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61175003A JPH0666416B2 (en) | 1986-07-24 | 1986-07-24 | Electrostatic protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61175003A JPH0666416B2 (en) | 1986-07-24 | 1986-07-24 | Electrostatic protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6331153A JPS6331153A (en) | 1988-02-09 |
| JPH0666416B2 true JPH0666416B2 (en) | 1994-08-24 |
Family
ID=15988516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61175003A Expired - Fee Related JPH0666416B2 (en) | 1986-07-24 | 1986-07-24 | Electrostatic protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666416B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0241621A (en) * | 1988-07-29 | 1990-02-09 | Matsushita Electron Corp | Semiconductor integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961223A (en) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | semiconductor integrated circuit |
-
1986
- 1986-07-24 JP JP61175003A patent/JPH0666416B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6331153A (en) | 1988-02-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |