JPH0680498B2 - Shared memory access control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a multi-system configured to couple a plurality of processing devices around a single global memory (shared memory), and in particular, to a program in the plurality of processing devices. The present invention relates to a shared memory control method suitable for parallel debugging.

A conventional multi-system is a plant database system in which a plurality of processing devices share the work and process them in parallel, and N processing devices that divide the work, centering on global data that aggregates information necessary for plant control. On the other hand, the aim is to realize a highly reliable system equipped with a single backup device.

FIG. 1 shows a hardware configuration example of a conventional multi-system. 1 to 3 are processing devices, 10 is a memory (global memory) shared by a plurality of processing devices, 20 is a bus mechanism for mutual communication between the processing devices, and 21 to 22 are input / output devices (30,3).
1), 23 to 24 are control mechanisms for sharing the file device (40, 41) among a plurality of processing devices.

The plant control information and the system management information are stored in a global memory 10 that can be accessed from a plurality of processing devices by an instruction word. Since the failure of the global memory 10 causes the system to go down, it has a dual configuration.

Each processing device uses the global memory 10 and the bus mechanism 20 for interconnecting processing devices to perform plant control in synchronization with each other.

When trying to debug the program by using the processing device of the standby standby system in parallel with the processing of the online control system,
This program accesses the plant control information in the global memory and destroys the information, resulting in the system down of the online control system.

In order not to bring down the system of the online control system,
The debugging system must be separated from the online control system.

For this reason, paying attention to the fact that the global memory has a redundant configuration, and when performing program debugging with one processing unit, change the global memory duplication to a single configuration, with one online system and the other There is a method of controlling so that it can be accessed only from the debugging system. However, this method has a drawback that it is not suitable for a multi-system including three or more systems.

It is an object of the present invention to provide a global memory access control system capable of performing program debugging on a plurality of processing devices in parallel, or debugging on a plurality of processing devices in parallel with processing of an online control system. It is in.

When a program is debugged by a processor, the debug system is separated from the online system.

At this time, the global memory is separated so that the debugging and online processors can physically access different data even if they have the same logical addresses.

By the way, the global memory contains plant control information,
And system management information is stored. For system management information, to maintain multi-system,
Since the debugging system and the online control system must share the same information, the system management information area is not separated. On the other hand, regarding the plant control information, the storage area is completely separated so that the debugging system and the online control system do not interfere with each other.

An embodiment of the present invention will be shown below in FIG. This embodiment relates to one utilizing an address translation mechanism in virtual memory control.

An address translation mechanism 101 (201) is provided for each processing device.
The address translation mechanism 101 (201) is a virtual memory 102 (202).
The above logical address is converted into a physical address on the main memory 103 (203) or on the global memory 10.

System management information area 10 in global memory 10
S and a brand control information area 10A are arranged. Similarly, the system management information area 102S (202S) and plant control information area 102A (202A) are also stored on the virtual memory 102 (202).
Are arranged.

In the online mode, 102S (202S) on the virtual memory of each processing device is associated with 10S on the global memory. And associate 102A (202A) with 10A. At this time, the global memory 10 functions as a shared memory.

Here, it is assumed that the operation mode of the processing device 2 is changed to the debugging mode.

In the debugging mode, the pseudo plant control information area 10B is arranged in the empty area on the global memory 10. Then, the correspondence between the plant control information area 202A on the virtual memory 202 of the processing device 2 and the global memory 10 is
Change from A to 10B. At this time, the plant control information area is separated by the online control system and the debugging system.

Although FIG. 2 shows an embodiment in which the number of processing apparatuses is two, the same applies to the case of three or more processing apparatuses.

FIG. 3 shows a physical address switching mechanism depending on the operation mode.

Each processing device is equipped with a MODE register 205 to manage the operation mode of the processing device. MODE = 0 is online mode,
MODE = 1 represents the debugging mode.

The address translation mechanism 201 uses the logical address 206 as the physical address.
Convert to 207. The logical address 206 consists of multiple signals, but it is divided into two and one is the logical page address.
2061, and the other is called an in-page address 2062. The logical page address 2061 is converted into a physical page address 2064, and the physical page address 2064 and the in-page address 2062 are combined to form a physical address 207.

It has two page tables 2012 and 2014 for storing physical page addresses corresponding to all the logical page addresses 2061 and a memory 2016 for storing them. Also, the register 20 that stores the start address of the page table 2012
11 and a register 2013 that stores the start address of the page table 2014.

The page table 2012 stores the physical page address in the online mode, and the page table 2014 stores the physical page address in the debugging mode.

Add the start address 2065 of the page table to the arbitrary logical page address 2061 and add the address 20 in the memory 2016.
The physical page address is read out from one of the page tables 2012 or 2014 and output to 2064 corresponding to the logical page address.

The MODE register 205 and the page table top address selector circuit 2015 select one of the two page tables 2012 and 2014.

That is, when the MODE register 205 is in the online mode, the start address 2011 of the page table 2012 is output to 2065, and the physical address in the online mode is read from the page table 2012 corresponding to an arbitrary logical page address 2061 2064. Output to.

When the MODE register 205 is in debugging mode, the start address 2013 of the page table 2014 is output to 2065, and the page table corresponding to any logical page address 2061 is output.
Read the physical address in debugging mode from 2014 20
Output to 64.

The contents of the memory 2016 and the registers 2011 and 2013 have a rewriting means that can be initialized and changed on the way by a program.

When starting an arbitrary processing device, the operation mode (online or debugging mode) is set in the MODE register 205 according to the instruction of the operator. Also, the conversion information for online 2011 and 2012 and the conversion information for debugging 2013 and 2014 are set, and the address conversion mechanism is initialized.

When shifting an arbitrary processing device from the online mode to the debugging mode, the one-sided online mode is shifted to the stop mode, the online processing is completely stopped, and then the debugging mode is started. The same applies when shifting from the debugging mode to the online mode.

Further, the address conversion information of 2011, 2012, 2013, 2014 has a failure of the processing device, and a copy is held in the file device.

As described above, according to the present invention, it is possible to easily separate the global memory and create the dedicated area for each processing device by using the address conversion mechanism of the virtual memory control. You will be able to debug your programs in parallel without affecting each other.

Further, even if the program is debugged by another processing device during the online control, the debugging system does not destroy the information of the online control system, so that the system down accident caused by it does not occur.

[Brief description of drawings]

FIG. 1 is a hardware configuration diagram of a multi-system, FIG. 2 is an explanatory diagram of a global memory separation method using an address translation mechanism of virtual memory control, and FIG. 3 is a block diagram of a physical address switching mechanism according to an operation mode. Is.

Claims (1)

[Claims] 1. In a multi-system, wherein a plurality of processing devices are configured to be coupled via a shared memory, each processing device is provided with an address translation device for converting a logical address for the shared memory into a physical address. ,
When each processing device operates normally, address conversion information for each processing device to access the shared area of the shared memory is set in the address conversion device of each processing device, and a certain processing device debugs the program. An access control method for a shared memory, characterized in that the address translation information for accessing the dedicated area other than the shared area is set to the address translation device of the processing device when performing the above.