JPH0681002B2 - Automatic gain control circuit - Google Patents

Description

The present invention relates to an automatic gain control circuit, and more particularly to an automatic gain control circuit suitable for sample value control.

〔Overview〕

The present invention is an automatic gain amplifier configured to sample a received signal that has been distorted by a transmission line, input it to a variable gain circuit, detect the peak value of its output waveform, and apply negative feedback to the variable gain circuit as a control signal. In the control circuit, the output of the variable gain circuit and the output obtained by delaying this output for T / 2 time are added, and then the peak value is detected. The value can be detected, stability is improved, and digitalization facilitates integration into an integrated circuit.

[Prior Art] Conventionally, in an automatic gain control circuit suitable for sample value control,
For example, The Bell System techntcal Journal, November 1982, 2
As shown on page 743, the peak value is detected for the output waveform of the automatic gain control circuit by the diode clip analog technology, and the variable gain circuit is controlled by the result.

[Problems to be solved by the invention]

The conventional automatic gain control circuit described above has a drawback in that the loop gain increases if the variable gain width is widened, and the stability of the system is lost. Further, since analog technology is used, it is difficult to form an integrated circuit and it is difficult to reduce the cost.

An object of the present invention is to provide an automatic gain control circuit which is suitable for a sample value control system, has high stability, and can be easily integrated into an integrated circuit by eliminating the above drawbacks.

[Means for solving problems]

The present invention relates to a sampling circuit for sampling a reception signal of a time slot T which is distorted by a transmission line, a variable gain circuit for inputting the output of the sampling circuit and performing gain control, and a peak of an output waveform of the variable gain circuit. In an automatic gain control circuit including a peak detection circuit for detecting a value and a control circuit for controlling the gain of the variable gain circuit according to the output of the peak detection circuit, the output of the variable gain circuit is input to delay T / 2 time. And a calculation circuit for adding the output of the delay circuit and the output of the variable gain circuit and outputting the sum to the peak detection circuit.

[Work]

The output waveform from the arithmetic circuit is the sum of the output of the variable gain circuit and the output of the delay circuit in which the phase of the output of this variable gain circuit is delayed, so that the waveform shows the time slot of the received signal. Letting T be the superposition of the output waveform of the variable gain circuit from -T to T and the output waveform of the delay circuit from 0 to 2T, and as a result, a waveform with a substantially constant amplitude between 0 and T is obtained. .

Therefore, if the sampling cycle of the sampling circuit is shorter than the time slot T, the output of the peak detection circuit can detect the correct level corresponding to the amplitude of the received signal, despite the deviation of the sampling phase.
It is possible to improve stability. Further, the delay circuit and the arithmetic circuit can be easily integrated into a digital circuit, and a circuit that is easy to be integrated as a whole can be realized.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a sampling circuit 1 for sampling a reception signal distorted by a transmission line, a variable gain circuit 2 for inputting an output of the sampling circuit 1 and performing gain control,
In an automatic gain control circuit including a peak detection circuit 5 that detects a peak value of an output waveform of the variable gain circuit 2 and a control circuit 6 that controls the gain of the variable gain circuit 2 according to the output of the peak detection circuit 5, A delay circuit 3 for receiving the output of the gain circuit 2 and delaying it by T / 2 time, and this delay circuit 3
And the output of the variable gain circuit 2 and the peak detection circuit 5 outputs the result. In addition, 7 is an input terminal and 8 is an output terminal.

The feature of the present invention resides in that the delay circuit 3 and the arithmetic circuit 4 are provided in FIG.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to the waveform charts of (c) and each part shown in FIG.

2A, 2B and 2C are waveform diagrams of the output A of the variable gain circuit 2, the output B of the delay circuit 3 and the output C of the arithmetic circuit 4, respectively, and the horizontal axis is the time axis. The vertical axis represents the amplitude, and T is the time slot of the received signal.

That is, the output C has a form in which the waveform of the output A and the waveform of the output B are superposed, and the section from 0 to T has a substantially constant amplitude value.

Therefore, in the peak detection circuit 5, by setting the sampling period in the sampling circuit 1 to be shorter than the time slot T, even if the sampling phase is deviated, a correct constant level corresponding to the received signal amplitude is obtained. Can be detected.

FIG. 3 is a waveform diagram of the output C showing this relationship. In the figure, output C ₀ is standard output, output C ₁ is below standard output,
The output C ₂ indicates an output higher than the standard. As a result, the peak detection circuit 5 detects a correct peak value corresponding to the amplitude value of the received signal, and controls the gain of the variable gain circuit 2 via the control circuit 6 so as to reach the standard value determined. To do.

The delay circuit 3 and the arithmetic circuit 4 can be realized by a digital circuit, which facilitates the integrated circuit of the entire circuit.

〔The invention's effect〕

As described above, the present invention can detect the correct peak value corresponding to the amplitude of the received signal regardless of the sampling phase, and has the effect of improving the stability.
Further, since digital circuits such as the delay circuit and the arithmetic circuit are used, there is an effect that the integrated circuit can be easily formed and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 2 (a), (b), (c) and FIG. 3 are output waveform charts of respective parts showing the operation. 1 ... Sampling circuit, 2 ... Variable gain circuit, 3 ...
Delay circuit, 4 ... Arithmetic circuit, 5 ... Peak detection circuit, 6
...... Control circuit, 7 ... Input terminal, 8 ... Output terminal, A to
C, C _{0 to} C ₂ ... Output.

Claims (1)

[Claims] 1. A time slot T distorted by a transmission line.
Circuit (1) for sampling the received signal of
A variable gain circuit (2) for inputting the output of the sampling circuit to perform gain control, a peak detection circuit (5) for detecting the peak value of the output waveform of the variable gain circuit, and an output of the peak detection circuit. In an automatic gain control circuit including a control circuit (6) for controlling the gain of the variable gain circuit, a delay circuit (3) for inputting the output of the variable gain circuit and delaying for T / 2 time, and an output of the delay circuit. An automatic gain control circuit comprising: an arithmetic circuit (5) for adding the output of the variable gain circuit to the peak detection circuit.