JPH0744535B2 - Data acquisition circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data acquisition circuit, and more particularly, to a digital communication device for communicating digital data, such that the sent digital data is acquired at an optimum timing. It relates to a data acquisition circuit.

[Prior Art] FIG. 6 is a schematic block diagram of a receiving unit in a conventional digital communication apparatus.

First, with reference to FIG. 6, a schematic configuration of a receiving unit in a conventional digital communication device will be described. Communication line 1
Is connected to the input of amplifier 2. The amplifier 2 amplifies the digital data transmitted to the communication line 1. The output of the amplifier 2 is given to the timing generation circuit 3 and the drain of the n-channel transistor 4. The timing generation circuit 3 generates a timing signal for turning on / off the n-channel transistor 4, and supplies this timing signal to the gate of the n-channel transistor 4. The source of the n-channel transistor 4 is connected to the frame synchronization detection circuit 5 and the data processing circuit 6. The frame synchronization detection circuit detects the frame synchronization of digital data, and the data processing circuit 6 processes the transmitted digital data.

FIG. 7 is a timing chart for explaining the operation of the receiving section shown in FIG.

Next, the operation of the receiving section shown in FIG. 6 will be described with reference to FIG. As shown in FIG. 7A, 100% duty digital data which constitutes one frame of 8 bits is transmitted to the communication line 1. Since this digital data is attenuated while being transmitted to the communication line 1, it is amplified by the amplifier 2. The timing generation circuit 3 generates a timing signal as shown in FIG. 7 (d) in synchronization with the digital data given from the output of the amplifier 2. The n-channel transistor 4 turns on and off according to the timing signal. When the n-channel transistor 4 is turned on, digital data is given to the frame synchronization detection circuit 5 and the data processing circuit 6, and the frame synchronization detection circuit 5 detects the frame synchronization.
The data processing circuit 6 processes the digital data.

[Problems to be Solved by the Invention] By the way, the waveform of digital data deteriorates while being transmitted to the communication line 1. That is, as compared with the waveform at the time of transmission as shown in FIG. 7 (b), the digital data has a rising and falling waveform at the time of being amplified by the amplifier 2 as shown in FIG. 7 (c). I'm blunt. For this reason, in the boundary portion between the previous bit and the subsequent bit of the digital data, for example, in the section x shown in FIG.
It becomes difficult to judge whether it is a level.

Therefore, the timing at which the n-channel transistor 4 is turned on and the data is taken in is generated by the timing generation circuit 3 so that the data is taken in while avoiding the portion where the rising and falling edges of the digital data are dull. It defines the timing of signals.

By the way, the dullness of the waveform of the digital data depends on the characteristics of the driver for transmitting the digital data on the communication line 1 or the transmitting side. For this reason, when the receiver is manufactured, the generation timing of the timing signal output from the timing generation circuit 3 must be set so that the test pulse is transmitted from the transmission side and the digital data can be captured at the optimum timing. Therefore, there is a problem that the timing setting becomes complicated.

Therefore, a main object of the present invention is to provide a data acquisition circuit capable of optimizing reception data acquisition timing during normal communication without sending a test pulse for timing optimization. .

[Means for Solving the Problem] The present invention relates to a digital communication device for communicating digital data, which is a data capturing circuit for capturing the transmitted digital data at an optimum timing. A plurality of timing signals with different timings are generated in synchronization, a plurality of switching means are switched according to each timing signal, data is output at each timing, and the frame synchronization of each output digital data is performed. The signal is detected, the signal with the best frame synchronization is discriminated, and the digital data is given to the data processing means for data processing.

[Operation] A data fetch circuit according to the present invention generates a plurality of different timing signals in synchronization with digital data, fetches data according to each timing signal, and obtains the digital data with the highest frame synchronization among the respective data. Since the data is discriminated and the data is output to the processing means, the optimum data acquisition timing can be determined during normal communication without sending the test pulse.

Embodiment of the Invention FIG. 1 is a schematic block diagram of an embodiment of the present invention.
2 is a block diagram of the timing generation circuit shown in FIG. 1, FIG. 3 is a block diagram of the frame synchronization detection circuit shown in FIG. 1, and FIG. 4 is a timing diagram shown in FIG. It is an electric circuit diagram of a discrimination circuit.

The configuration of an embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the communication line 1, the amplifier 2, and the data processing circuit 6 are the same as those in FIG. 6 described above. The digital data amplified by the amplifier 2 is supplied to the timing generation circuit 30 and also to the drains of the n-channel transistors 41, 42 and 43. The timing generation circuit 30 generates three timing signals having different timings in synchronism with the given digital data to generate n-channel transistors 41, 42.
And give to each gate of 43. The sources of the n-channel transistors 41, 42 and 43 are applied to the timing discrimination circuit 7 and the frame synchronization detection circuits 51, 52 and 53, respectively. The frame synchronization detection circuits 51, 52 and 53 detect the frame synchronization of the digital data output from the n-channel transistors 41, 42 and 43, respectively, and apply respective detection signals to the timing discrimination circuit 7.

Here, a specific configuration of the timing generation circuit 30 will be described with reference to FIG. The PLL circuit 31 is supplied with the digital data amplified by the amplifier 2 shown in FIG. 1 and the clock signal a generated by a clock oscillator (not shown). The PLL circuit 31 generates a clock signal b which is synchronized with the input digital data. The clock signal a is selected so that its frequency is sufficiently higher than that of the clock signal b. The clock signal b generated by the PLL circuit 31 is given to the counter 32. counter
32 counts the clock signal a and is reset every time the clock signal b is applied. The count output of the counter 32 is given to the decoder 33. The decoder 33 decodes the count output of the counter 32 and outputs a plurality of timing signals which are at the "H" level for one cycle of the clock signal b, that is, once for one cycle of the data input width. To do.

Next, the configuration of the frame synchronization detection circuit 51 will be described with reference to FIG. The frame synchronization detection circuit 51 includes a latch circuit 511, a frame bit detection circuit 512, and a frame synchronization determination circuit 513. Digital data derived from the n-channel transistor 41 is applied to the latch circuit 511, and this digital data is latched. The latched digital data is supplied to the frame bit detection circuit 512. The clock signal b is given from the timing generation circuit 30 to the frame bit detection circuit 512, and the frame bit indicating the head of the frame is detected based on the clock signal b. Then, the frame bit detection circuit 512 gives the detected frame bit to the frame synchronization determination circuit 513. This frame synchronization determination circuit 5
A clock signal b is given to 13, and the frame synchronization determination circuit 513 determines the frame synchronization based on the clock signal b and the frame bit given from the frame bit detection circuit 512, and the determination output is the timing determination. It is given to the circuit 7.

Next, the configuration of the timing discrimination circuit 7 will be described with reference to FIG. The timing discrimination circuit 7 is, for example, 3
N-channel transistors 71, 72 and 73, and n-channel transistors 71, 72 and 73
Each drain of has an n-channel transistor 4
Digital data output from 1, 42 and 43 are applied respectively, and frame sync detection signals output from the frame sync detection circuits 51, 52 and 53 are applied to respective gates. Each of the n-channel transistors 71, 72 and 73 becomes conductive in response to the frame sync detection signal from the frame sync detection circuit and outputs digital data to the data processing circuit 6.

FIG. 5 is a timing chart for explaining the operation of the embodiment of the present invention.

Next, the specific operation of the embodiment of the present invention will be described with reference to FIGS. The digital data transmitted to the communication line 1 has two consecutive bits from the beginning as the frame bit for finding the beginning position of the frame in the frame structure shown in FIG. Other than this, the frame structure has a feature that "1" does not continue.
Digital data having such a frame structure is used for the communication line 1.
When it is transmitted to the amplifier and amplified by the amplifier 2, it is attenuated during the transmission, and the rising and falling waveforms are blunted and output as shown in FIG. 5 (c). Timing generation circuit 30
The PLL circuit 31 generates a clock signal b based on the input digital data and the clock signal a. Then, the counter 32 counts the clock signal b, the count output is given to the decoder 33, and the data fetch timing signals 1 and 2 shown in FIGS. 5 (d), 5 (e) and 5 (f) are supplied from the decoder 33. , 3 is output.

As is apparent from FIGS. 5 (d), (e), and (f), the data acquisition timing signals 1 and 3 do not correspond to the two consecutive "1" frame bits of the received digital data. That is, only the data fetch timing signal 2 corresponds to the frame bit of "1" in which 2 bits are consecutive. For this reason, two consecutive "1" frame bits appear only in the output of the n-channel transistor 42 which is turned on by the data fetch timing signal 2.
Then, the latch circuit 511 of the frame synchronization detection circuit 52 latches the frame bit of the digital data, and based on the latch output, the frame bit detection circuit 512 detects the frame bit and supplies it to the frame synchronization determination circuit 513. The frame synchronization determination circuit 513 determines that the frame synchronization has been performed when two frame bits are applied, and applies a frame synchronization determination signal to the gate of the n-channel transistor 72 of the timing determination circuit 7. In response, n-channel transistor 72 becomes conductive, and the digital data given through n-channel transistor 42 is output and given to data processing circuit 6.

On the other hand, the frame synchronization detection circuits 51 and 53 do not output the frame synchronization determination signal because they do not detect 2 frame bits. Therefore, the timing discrimination circuit 7
The n-channel transistors 71 and 73 are not turned on, and the digital data given through the n-channel transistors 41 and 43 are not output.

It should be noted that in the above embodiment, three frame synchronization detection circuits are used.
51, 52 and 53 are provided and three data capture timing signals are output from the timing generation circuit 30. However, the number of frame synchronization detection circuits is not limited to this, and an arbitrary number of frame synchronization detection circuits are provided. The data fetch timing signal may be generated.

Further, in the above-described embodiment, three frame synchronization detection circuits are used.
It generated 51, 52 and 53 and three data acquisition timing signals so that they would operate simultaneously in parallel.
Even if one frame synchronization detection circuit is provided and the data acquisition timing signal is changed with time, the same effect can be obtained.

[Effects of the Invention] As described above, according to the present invention, a plurality of different timing signals are generated in synchronization with digital data, the digital data is taken in at each timing, and the frame synchronization of the digital data is performed. Since the configuration is such that only the acquired data is taken in, it is possible to eliminate the complexity of determining the timing of generating the timing signal in the receiving section by transmitting the test pulse as in the conventional case.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of the timing generation circuit shown in FIG. FIG. 3 is a block diagram of the frame synchronization detection circuit shown in FIG. FIG. 4 is a specific electric circuit diagram of the timing discrimination circuit shown in FIG. FIG. 5 is a timing chart for explaining the specific operation of the embodiment of the present invention. FIG. 6 is a schematic block diagram of a conventional receiver. FIG. 7 is a timing chart for explaining the operation of the conventional receiving section. In the figure, 1 is a communication line, 2 is an amplifier, 6 is a data processing circuit, 7 is a timing determination circuit, 30 is a timing generation circuit, 31 is a PLL circuit, 32 is a counter, 33 is a decoder, and 41-4.
3, 71 to 73 are n-channel transistors, 51, 52 and 53 are frame synchronization detection circuits, 511 is a latch circuit, 512 is a frame bit detection circuit, and 513 is a frame synchronization determination circuit.

Claims (1)

[Claims] 1. A digital communication device for communicating digital data, which is a data fetch circuit for fetching sent digital data at an optimum timing, wherein a plurality of data fetch circuits are synchronized with the sent digital data. Timing signal generating means for generating timing signals of different timing, switching according to each of a plurality of different timing signals generated from the timing signal generating means,
A plurality of switching means for outputting the digital data, a frame synchronization detecting means for detecting frame synchronization of the respective digital data output from the plurality of switching means, the switching according to a synchronization detection output of the frame synchronization detecting means A discriminating means for discriminating the most frame-synchronized signal of the digital data outputted from the means and outputting the digital data; and a data processing means for processing the digital data outputted from the discriminating means. A data acquisition circuit equipped.