JPH0682678B2 - Bipolar transistor manufacturing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a bipolar transistor.

2. Description of the Related Art Trends in semiconductor devices include high-density integration, high speed, and high frequency. In a bipolar transistor, the basic performance factor when considering higher frequencies is the cutoff frequency t. t is generally expressed by the following equation.

t = 1 / (2πτec) (1) τec = τe + τb + τc + τc '(2) where τe is the emitter depletion layer charging time, τb is the base transit time, τc is the collector depletion layer transit time, and τc' is the collector. Depletion layer charging time.

In equation (2), τe and τc 'are proportional to the resistance and capacitance of the emitter region and collector region. When the transistor size is reduced by miniaturization in order to reduce the capacitance, the resistance increases in inverse proportion to the area, so τe and τc ′ increase and the value of t decreases. This resistance component is represented by the sum of the internal resistance of each region and the contact resistance of the ohmic electrode provided in each region.
Therefore, the reduction of contact resistance and the reduction of capacitance are necessary items for increasing the frequency of bipolar transistors.

In the case of a trapezoidal bipolar transistor having a conventional multiple emitter electrode / single base electrode, the emitter electrode is
It was formed on the emitter region by alignment. Second example
Shown in the figure.

A collector region 4, a base region 3 and two emitter regions 2 are sequentially formed on a semiconductor substrate 1, and a collector electrode 7, a base electrode 6 and an emitter electrode 5 which are in ohmic contact with each other are formed on each region (for example, respectively). IEICE Technical Report, Electronic Devices 86-107, pages 21).

Problems to be Solved by the Invention However, in the above-described configuration, the emitter electrode of the uppermost layer is formed on the emitter region in alignment, so that the area of the emitter electrode becomes smaller than the area of the emitter region.
As miniaturization of the transistor progresses, it becomes difficult to obtain a sufficiently low contact resistance, and a capacitance exists in an unnecessary collector region directly below the base electrode, which hinders high frequency operation. In addition, the yield is lowered due to the formation of the alignment.

In particular, making the emitter region on the substrate side is an effective method for reducing the wiring distance at the time of integration, but if the emitter region and the collector region are simply exchanged in the conventional configuration, the A good transistor cannot be obtained due to the unnecessary emitter region just below the electrode.

The present invention greatly improves the above conventional problems,
To provide a method for manufacturing a bipolar transistor having a structure in which an unnecessary emitter region just below a base electrode is insulated with an emitter region on the substrate side and an increase in contact resistance due to a reduction in area is eliminated, and the yield is also improved. With the goal.

Means for Solving the Problems In order to solve the above problems, a method for manufacturing a bipolar transistor according to the present invention comprises a step of sequentially growing an emitter layer, a base layer and a collector layer on a semiconductor substrate, and a step of growing the collector layer on the collector layer. Etching the collector layer and the base layer until the emitter layer is exposed by the mask formed in step 1 to form a first inverted trapezoid including the collector and the base; and forming a collector electrode on the entire surface of the collector layer. Simultaneously performing the self-aligned formation and the self-aligned formation of an emitter electrode on the emitter layer using the first inverted trapezoid as a mask; and forming the first inverted trapezoidal collector layer on the emitter layer. Etching until the base layer is exposed to form a second inverted trapezoid including the collector layer on the first inverted trapezoidal base layer; and the second inverted trapezoid. Shape as a mask, forming an insulating region in the first inverted trapezoidal emitter layer, and forming a base on the first inverted trapezoidal base layer in a self-aligned manner with the second inverted trapezoidal mask as a mask. And a step of forming an electrode.

The bipolar transistor having the above structure has a collector electrode having the same area as that of the collector region when compared with a bipolar transistor having the same collector region area as the conventional structure. The resistance in each region can be made lower because the upper limit is minimized and the other electrodes are formed by self-alignment. Furthermore, with the emitter region on the substrate side,
Since the insulating region is formed in the unnecessary emitter region just below the base electrode, leakage current and capacitance can be reduced, and a transistor suitable for integration can be provided. The self-alignment also improves the yield.

Example One example of a method for manufacturing a bipolar transistor of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of an npn-type bipolar transistor according to an embodiment of the present invention. First, on the semiconductor substrate 31,
An n-type impurity-containing emitter layer to be the emitter region 34, a p-type impurity-containing base layer to be the base region 33, and an n-type impurity-containing collector layer to be the collector region 32 are sequentially formed by film growth. A resist 71 is formed on the portion to be formed so that the cross-sectional direction has an inverted trapezoidal shape ([011] direction for gallium arsenide crystal), and anisotropic etching (for wet etching of gallium arsenide crystal, for example, sulfuric acid / peroxidation Emitter area using hydrogen / water (1:12)
Etch to 34. After removing the resist 71, n
Type ohmic metal (in the case of gallium arsenide crystal, for example, gold germanium) is vapor-deposited on the entire surface, and the collector electrode 62 and the emitter electrode 64 are simultaneously formed on the collector region 32 and the emitter region 34 by self-alignment using the inverted trapezoidal shape. To do. Next, a hole is formed in the collector electrode 62 with a resist 72, the electrode is etched (potassium iodide solution in the case of a gold system) and the collector region 32 is anisotropically etched to locate the base region 33. . The resist 72 is removed, and heat treatment is performed to alloy the collector electrode 62 and the emitter electrode 64 to form an ohmic electrode. Next, using the collector electrode 62 and the emitter electrode 64 as a mask, deep ion implantation (for example, hydrogen ions) is performed into the emitter region 34 immediately below the base region 33 to form an insulating region 44. Finally, a p-type ohmic metal (for example, gallium arsenide crystal, for example, gold zinc) is vapor-deposited on the entire surface, a base electrode 93 is formed on the base region 33 by self-alignment, and heat treatment is performed to alloy the base electrode 93. As a result, an ohmic electrode is obtained. In the above process, the order of heat treatment and ion implantation of the collector electrode 62 and the emitter electrode 64 may be changed. The npn-type bipolar transistor in this embodiment is completed in the above order.

The above manufacturing process can also be applied to a heterojunction bipolar transistor having higher high frequency characteristics,
In this case, a semiconductor having a forbidden band width larger than that of the semiconductor used for the base during film growth may be used for the emitter.

EFFECTS OF THE INVENTION As described above, according to the method of manufacturing a bipolar transistor having the structure of the present invention, the area of the collector electrode can be made equal to the area of the collector region by self-alignment, so that the contact resistance is structurally minimized. In addition, the base electrode and the emitter electrode can be formed by self-alignment, which prevents an increase in resistance in each region which is a problem in miniaturization of the bipolar transistor. Furthermore, since the emitter region is on the substrate side and an insulating region is formed in an unnecessary emitter region directly below the base electrode, leakage current and capacitance can be reduced, which greatly contributes to higher frequency bipolar transistors and contributes to integration. A suitable transistor can be provided, and the self-alignment also improves the yield. Also,
The same manufacturing process can be used to manufacture a comb-type transistor having a plurality of collectors / bases.

[Brief description of drawings]

FIG. 1 is a sectional view showing the construction of an embodiment of the present invention, and FIG. 2 is a sectional view showing the construction of a conventional multi-emitter / single-base bipolar transistor. 31 ... Semiconductor substrate, 32 ... Collector region, 33 ... Base region, 34 ... Emitter region, 44 ... Insulation region, 71, 72 ...
… Resist, 62 …… Collector electrode, 93 …… Base electrode,
64 …… Emitter electrode.

Front Page Continuation (72) Inventor Manabu Yanagihara 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP 59-210669 (JP, A) JP 49-43583 (JP, A) JP 62-18761 (JP, A) IEICE Technical Report Vol. 85, No. 263 P.I. 17-23 SSD85-111 1986.1.21

Claims (2)

[Claims] 1. An emitter layer, a base layer, and
The collector layer and the base layer are etched until the emitter layer is exposed by the step of sequentially growing the collector layer and the mask formed on the collector layer to form a first inverted trapezoid including the collector and the base. And a collector electrode is formed on the entire surface of the collector layer in a self-aligned manner, and an emitter electrode made of the same material as the collector electrode is self-aligned on the emitter layer using the first inverted trapezoid as a mask. Simultaneously forming in a conformal manner, and etching the first inverted trapezoidal collector layer until the base layer is exposed, and including the collector layer on the first inverted trapezoidal base layer. Forming a second inverted trapezoid; forming an insulating region in the emitter layer of the first inverted trapezoid using the second inverted trapezoid as a mask; Forming a base electrode made of a material different from that of the emitter electrode and the collector electrode in a self-aligned manner on the base layer using the second inverted trapezoid as a mask. Production method. 2. The method for manufacturing a bipolar transistor according to claim 1, wherein a semiconductor having a forbidden band width larger than that of the semiconductor used for the base layer is used for the emitter layer.