JPH0683040B2 - Selection control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selection control circuit for controlling a selection circuit to select one of output signals of a plurality of circuits, particularly when an initialization signal is given. Relates to a so-called switchback control selection control circuit for selecting an output signal of a specific circuit among the plurality of circuits.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a device having a conventional selection control circuit. Generally, various circuits can be configured in the selection control circuit according to the number of circuits to be selected, but FIG. 3 shows the simplest case in which the number of circuits to be selected is two. Selection control circuit. In FIG. 3, 10 and 20 are circuits having the same function, 100 is an output signal of the circuit 10, and 200 is an output signal of the circuit 20. 150
Is a failure status signal of the circuit 10 and 250 is a failure status signal of the circuit 20, which are applied to the failure status signal receiving terminals 1 and 2 of the selection control circuit 40, respectively.

These fault state signals 150 and 250 are at the logic level "0" when the circuit is in the fault state and at the logic level "1" when the circuit is in the normal state.

Reference numeral 30 denotes a selection circuit, which outputs the output signal 100 of the circuit 10 when the selection control signal 400 given from the output terminal 4 of the selection control circuit 40 is at the logic level "1" and the circuit 2 when the selection control signal 400 is at the logic level "0".
The output signal 200 of 0 is selected and output to the output terminal 5.

For example, as shown in the figure, the selection control circuit 40 includes a flip-flop 41 that outputs a signal of a logic level “1” that is set when the failure state signal 150 from the circuit 10 is a logic level “0”,
Similarly, the fault status signal 250 from the circuit 20 has a logic level "0".
In the case of, the flip-flop 42 that outputs the signal of the logic level “1”, the inverter circuit 43 that inverts the output signal of the flip-flop 42, and this inverter circuit 43
Of the output signal of the flip-flop 41 and the output signal of the flip-flop 41.

An initialization signal 350 is given from the initialization signal input terminal 3 to the reset input terminals of the two flip-flops 41 and 42, and while the fault status signals 150 and 250 from each circuit are at the logic level "1", When the initialization signal 350 of "0" is given, the output logic level of each flip-flop becomes "0".

Next, the operation of this conventional switching control circuit will be described.

When the two circuits 10 and 20 are normal, the failure state signals 150 and 250 of the logic level "1" are given from the both circuits to the two flip-flops 41 and 42, and in this state, the initialization signal 300 is the logic level "0". Then, both flip-flops are in the initial state and their outputs are at the logic level "0".

The output signal of the flip-flop 42 is inverted by the inverter circuit 43 to become "1", and is applied to one input terminal of the gate circuit 44. On the other hand, the output signal of the flip-flop 41 is directly applied to the other input terminal of the gate circuit 44. Therefore, in this initial state, the output signal level of the gate circuit 44, which is the output signal of the selection control circuit 40, becomes "1", and the selection circuit
30 selects the signal from circuit 10.

When the circuit 10 fails and the logic level of the fault status signal 150 of this circuit becomes "0", the flip-flop 41 is inverted and its output logic level becomes "1". This result selection control circuit
The output logic level of 40 becomes "0", and the selection circuit 30 selects the output signal of the normal circuit 20.

Similarly, when the relationship between the failure states of the two circuits 10 and 20 and the output signal of the selection control circuit 40 is obtained in the same manner, when the circuit 10 is normal and the circuit 20 is defective, the selection control circuit 40 sets the logic level "1". Further, when both the circuit 10 and the circuit 20 have a failure, the output logic level becomes "1". Therefore, this selection control circuit generates a selection control signal 400 for selecting the circuit 10 when the circuit 10 is normal or when the two circuits 10 and 20 both fail, and when the circuit 10 is faulty and the circuit 20 is normal. Therefore, the selection control signal 400 for selecting the normal circuit 20 is generated, and the selection control in which the circuit 10 is set in advance as the higher priority is realized. Here, flip-flops 41, 4
As described above, 2 does not invert the output even if the initialization signal 350 is at the logic level "0" while the failure status signals 150 and 250 from each circuit are "0", so the failure status signal is output continuously. In this case, the selection control is not affected even if the initialization signal 350 is added at any time.

Next, the initialization (cutback) operation in this conventional selection control circuit will be described. Circuit 20 is in normal condition,
When the circuit 10 is in the failure state, the selection control circuit 40 is operated as described above.
Is a selection control signal 40 that selects the output signal of the normal circuit 20
0 is applied to the selection circuit 30. After the failure of the circuit 10 is recovered from this state and the logic level of the failure status signal 150 from the circuit 10 changes from "0" to "1", the initialization signal of the logic level "0" is input to the initialization signal input terminal 3. Immediately after giving 350, the selection control signal 400 is inverted and its logic level changes from "0" to "1", and the output signal of the circuit 10 is selected. Where circuit 10
Similarly, if the initialization signal of logic level “0” is applied before the failure of the circuit is recovered and then the circuit 10 recovers,
The selection control signal 400 is inverted at the same time as the recovery of, and its logic level changes from “0” to “1”.

As described above, in the conventional selection control circuit, the initialization control is determined only by the failure state signals from both circuits 10 and 20 at the time when the initialization signal is given. Therefore, the failure state of the circuit 10 does not become a continuous state at one time, and the failure state signal 150 changes in a short time such as “0” → “1” → “0” → “1”. If the initialization signal of logic level "0" is added, the selection control signal 400 is also "0".
→ "1" → "0" → "1" ... Change, and the selection circuit 30 performs many switching and switching back in a short time.

FIG. 4 is a waveform diagram showing the operation of each part of the conventional selection control circuit for explaining this pattern. In FIG. 4, the circuit 20 is always normal and therefore the fault status signal 250 from the circuit 20
Is always "1". When the circuit 10 fails at time t _{0 and the} clock-like failure state signal 150 is output as shown in the figure, the selection control circuit 40 outputs the selection control signal 400 for selecting the circuit 20 at the same time. If the initialization signal 300 is added to the time t ₁ in this state, the selection control signal 400 immediately inverts to the logic level “1” when the failure state signal 150 becomes the logic level “1” after this time. . Since the fault status signal 150 is clock-shaped as described above, the selection signal 400 is also clock-shaped while the initialization signal 350 is being applied as shown.

[Problems to be solved by the invention]

Generally, when looking at the failure occurrence status of a circuit on the time axis, it is rare that a failure occurs or recovers at one time.For example, when looking at a failure occurrence, there is no sudden change from a normal state to a sudden failure state. In many cases, after the state and the fault state are repeated, the state eventually becomes a steady fault state.

In general, it is extremely difficult to exactly match the failure detection threshold with the normality of the circuit, and the circuit output immediately before the failure detection is not always normal in many cases.

By the way, since the circuit failure state signal changes in principle after detecting a circuit failure, the output signal of the circuit immediately before the failure state signal is output contains some abnormality. Therefore, in a device that performs selection control based on a failure state signal, the signal immediately before the selection circuit operates contains some abnormality.

As described above, in a general device, the output signal of the circuit immediately after the detection of the failure or the recovery is often not always normal, and the change in the failure state does not become a steady state change at one time. In the device which selects the output of the normal circuit according to the failure state of the circuit and tries to maintain the normality of the device output, it is necessary to reduce the number of selection operations of the selection circuit generated in one failure as much as possible. .

However, in general, the initialization signal is added by the maintenance person at any time at any time, so in the conventional selection control circuit, even if the failure status signal of the circuit is intermittent as described above, the initialization signal is Since the voltage is applied, a large number of selection operations occur during this period, resulting in a significant deterioration of the output signal quality.

An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional circuit with a simple configuration, and to prevent unnecessary selection operation even if an initialization signal is given when the failure state of the circuit is intermittent. It is to provide a selection control circuit.

[Means for solving problems]

The present invention controls a selection circuit to select one of output signals of a plurality of circuits, and when an initialization signal is given, selects an output signal of a specific circuit among the plurality of circuits. In the selection control circuit for controlling the selection circuit, a time limit circuit that is activated by a failure state signal indicating that the specific circuit has a failure and outputs a time limit signal for a predetermined time, and the time limit circuit is the time limit circuit. And a gate circuit that blocks the initialization signal when the signal is output.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 1 is a receiving terminal for a failure status signal 150 from the first circuit (corresponding to the circuit 10 in FIG. 3), and 2 is a failure status signal from the second circuit (corresponding to the circuit 20 in FIG. 3). It is a receiving terminal of 250, and a signal of logic level "1" is given when each circuit is normal, and a logic level "0" is given when each circuit is in a failure state.

41 is a flip-flop which is set when the fault status signal 150 is at the logic level "0" and outputs a logic level "1", and 42 is set when the fault state signal 250 is at the logic level "0" and is at the logic level "1" Is a flip-flop that outputs 43
Is an inverter circuit that inverts the output signal of the flip-flop 42, 44 is a gate circuit that takes the logical product of the output signal of the flip-flop 41 and the output signal of the inverter circuit 43,
The output of this gate circuit is output from the selection control signal output terminal 4 as the selection signal output of the selection control circuit of the present invention.

Reference numeral 45 is a time circuit activated by the failure state signal 150 from the first circuit, and is realized by, for example, a retriggerable mono multivibrator. In this embodiment, the output signal 450 which becomes the logic level "1" for the time T from the time when the failure state signal 150 changes from the logic level "1" to "0" and becomes the logic level "0" after the time T is output. It shall be output.

46 designates the output signal 450 of the time limit circuit 45 as one input signal,
It is a gate circuit which receives the initialization signal 350 given from the initialization signal input terminal 3 as the other input, and blocks the initialization signal while the output signal 450 of the time circuit 45 is at the logic level "1",
Outputs a signal of logic level "1". The output signal 460 of the gate circuit 46 is applied to the reset inputs of the flip-flops 41 and 42, and the fault status signals 150 and 250 are set to the logic level "1".
When the output signal 460 becomes the logic level "0" while the above, the two flip-flops 41 and 42 are initialized and output the signal of the logic level "0".

Next, the operation of the selection control circuit of this embodiment having the above configuration will be described.

Since both the first and second circuits are normal and the outputs of the flip-flops 41 and 42 are both "0" when the initialization is completed, the control signal output terminal 4 outputs a logic level "1". The selection signal 400 is output.

When the first circuit fails, the failure state signal 150 from the first circuit becomes the logic level "0", so the output of the flip-flop 41 becomes the logic level "1". At this time, the output of the flip-flop 42 still outputs the signal of the logical level "0", so that the selection signal output terminal 4 outputs the selection signal 400 of the logical level "0". Similarly, when the relationship between the failure states of the two circuits and the selection signal output is obtained,
Circuit is normal (logic level of fault status signal 150 is "1")
If the second circuit is faulty (the logic level of fault status signal 250 is "0") and both circuits are faulty (both fault status signals 150 and 250 are logic level "0"), the logic level is "1". Selection signal 400 is output.

Therefore, this embodiment realizes the selection control in which the first circuit is set in advance as the upper order, like the conventional selection control circuit shown in FIG.

Next, the initialization (reverting) operation will be described. When the first circuit of the higher priority has failed, the failure status signal 150 becomes the logic level "0" as described above, and the flip-flop 4
1 is set and outputs a logic level "1" and holds this state, so that the first circuit recovers and the failure state signal 15
The selection control signal 400 does not change even if the logic level of 0 becomes "1". Here, the failure state signal 150 is also given to the time limit circuit 45, and when a failure occurs, that is, when the failure state signal 150 changes from the logic level “1” to “0”, the logic level for the time T from this change time. The output signal 450 of "1" is output. This signal is input to one input terminal of the gate circuit 46, and while the logic level of this signal is "1", the output signal 460 is output regardless of the logic level of the signal applied to the other input terminal. Becomes a logic level "1". Therefore, since the initialization signal 350 is blocked by the gate circuit 46 and is not transmitted to the flip-flops 41 and 42 for the time T from the time when the fault status signal 150 changes from "1" to "0", even if the first signal
Even if the circuit of FIG. 3 is immediately restored and the initialization signal 350 is applied, the flip-flops 41 and 42 are not reset and inverted, and thus the selection control signal 400 does not change. Here, since the time limit circuit 45 generates an output signal of a prescribed time limit T for each change of the given fault condition signal 150,
When the failure state signal 150 changes in a cycle shorter than the time limit T, the output signal 450 is always "1",
Even if the initialization signal 350 is given during this period, the initialization operation is not activated.

FIG. 2 is a waveform diagram for explaining the operation of each part of the selection control circuit of this embodiment described above.

When the first circuit fails at time t ₀ while the failure status signal 250 of the second circuit indicates the normal status and the failure status signal 150 becomes the logic level “0”, as described above, the selection control signal The 400 immediately inverts and sends out a logic level "0".

The fault status signal 150 from the first circuit, which is a predetermined specific circuit, activates the timed circuit 45 when a circuit fault occurs. In the time limit circuit 45, the fault status signal 150 is "1" → "0"
Since a signal of which the time logic level "1" continues for T is generated every time the signal changes, the output signal of the timing circuit 45 is output when the failure state changes in a cycle shorter than T time as shown in the figure.
450 constantly goes to logic level "1" and the fault status signal 150
Logic level "0" after T time since the last change of
Return to.

While the signal 450 is at the logic level “1”, even if the initialization signal 350 is given, it is blocked by the gate circuit 46. Therefore, even if the initialization signal is given at the time t ₁ , the selection control signal 400 does not change immediately. , The change of the failure state signal 150 is terminated, and changes after t ₂ when the circuit 10 is in the stable state.

〔The invention's effect〕

As described above, in the selection control circuit of the present invention, the time limit circuit is activated by the failure state signal from the predetermined specific circuit, and the initialization signal is blocked by the output signal of this time limit circuit. Is changed in a short cycle, unnecessary initialization (reverting) operation is not performed, and the initialization operation is performed after the circuit is completely recovered.

Therefore, according to the selection control circuit of the present invention, even if the failure state is intermittent, such as when the circuit fails incompletely or its operation becomes unstable, the selection changing operation is unnecessary. The output signal quality of the device can be improved without being returned.

[Brief description of drawings]

1 is a block diagram showing the configuration of a selection control circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the selection control circuit of FIG. 1, and FIG. 3 is a conventional selection control circuit. FIG. 4 is a block diagram showing the configuration of a device that selects and outputs one of the two circuits, and FIG. 4 is a waveform diagram for explaining the operation of the conventional selection control circuit shown in FIG. 1,2 …… Fault status signal receiving terminal 3 …… Initialization signal input terminal 4 …… Selection control signal output terminal 5 …… Device output terminal 10,20 …… Circuit to be selected 30 …… Selection circuit 40… ... Selection control circuit 41,42 ... Flip-flop 43 ... Inverter circuit 44,46 ... Gate circuit 45 ... Time circuit

Claims (1)

[Claims] 1. When a selection circuit is controlled to select one of the output signals of a plurality of circuits and an initialization signal is given,
In a selection control circuit that controls the selection circuit to select an output signal of a specific circuit among the plurality of circuits, activated by a failure state signal indicating that the specific circuit has failed, and a predetermined time A selection control circuit comprising: a time limit circuit that outputs a time limit signal; and a gate circuit that blocks the initialization signal when the time limit circuit outputs the time limit signal.