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JPH07101973B2 - Voltage fluctuation suppression device - Google Patents
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JPH07101973B2 - Voltage fluctuation suppression device - Google Patents

Voltage fluctuation suppression device

Info

Publication number
JPH07101973B2
JPH07101973B2 JP58059582A JP5958283A JPH07101973B2 JP H07101973 B2 JPH07101973 B2 JP H07101973B2 JP 58059582 A JP58059582 A JP 58059582A JP 5958283 A JP5958283 A JP 5958283A JP H07101973 B2 JPH07101973 B2 JP H07101973B2
Authority
JP
Japan
Prior art keywords
voltage
voltage fluctuation
phase
reactor
fluctuations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58059582A
Other languages
Japanese (ja)
Other versions
JPS59185124A (en
Inventor
惇 西台
信 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP58059582A priority Critical patent/JPH07101973B2/en
Publication of JPS59185124A publication Critical patent/JPS59185124A/en
Publication of JPH07101973B2 publication Critical patent/JPH07101973B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30Reactive power compensation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/50Arrangements for eliminating or reducing asymmetry in polyphase networks

Landscapes

  • Supply And Distribution Of Alternating Current (AREA)
  • Control Of Electrical Variables (AREA)

Description

【発明の詳細な説明】 〔技術分野〕 本発明は電力系統の母線電圧が不平衡かつ急峻に変動し
ている場合にも母線電圧変動抑制のできる、サイリスタ
制御リアクトルと並列コンデンサよりなる電圧変動抑制
装置に関する。
Description: TECHNICAL FIELD The present invention is capable of suppressing bus voltage fluctuation even when the bus voltage of the power system is unbalanced and sharply fluctuated, and suppresses voltage fluctuation composed of a thyristor control reactor and a parallel capacitor. Regarding the device.

〔発明の目的〕[Object of the Invention]

第1図に電圧変動抑制装置の一例を示す。図において4
は直列リアクトルであり、5はサイリスタスイッチであ
り、直列リアクトル4とサイリスタスイッチ5は直列に
接続され、これに並列にコンデンサ6が接続される。
FIG. 1 shows an example of the voltage fluctuation suppressing device. 4 in the figure
Is a series reactor, 5 is a thyristor switch, the series reactor 4 and the thyristor switch 5 are connected in series, and the capacitor 6 is connected in parallel thereto.

1は無限大母線を示し、2は電源インピーダンスを示
し、3は設置母線を示す。設置母線3に対し、PT7およ
び前記PT7の出力信号をうけるサイリスタ制御装置8が
接続される。81は電圧検出器であり、その出力は減算器
82において、基準電圧Vrefと比較され、信号△Vu−vは
調節器83に入力され、パルス発生器84より点弧制御パル
スを発生し、サイリスタスイッチ5を制御し、直列リア
クトル4の通電制御を行って消費無効電力を調節し、電
圧変動を抑制する。
1 indicates an infinite bus, 2 indicates a power source impedance, and 3 indicates an installation bus. A PT7 and a thyristor control device 8 which receives an output signal of the PT7 are connected to the installation bus bar 3. 81 is a voltage detector, the output of which is a subtractor
At 82, the reference voltage Vref is compared, and the signal ΔVu-v is input to the regulator 83, an ignition control pulse is generated from the pulse generator 84, the thyristor switch 5 is controlled, and the energization control of the series reactor 4 is performed. It adjusts the reactive power consumption and suppresses voltage fluctuations.

このようにサイリスタスイッチで制御される直列リアク
トル回路は、詳細には第2図のような3相構成となって
おり、実際には前記第1図の電圧検出器81は母線3の線
間電圧を検出し、各相のリアクトルを制御し、各相の線
間電圧を一定とするように制御している。
The series reactor circuit controlled by the thyristor switch has a three-phase structure as shown in FIG. 2 in detail, and the voltage detector 81 shown in FIG. Is detected, the reactor of each phase is controlled, and the line voltage of each phase is controlled to be constant.

しかし、不平衡負荷による電圧変化は、関係のない他の
相にも影響し、各線間電圧の変化を検出しただけでは次
のような問題がある。
However, the voltage change due to the unbalanced load also affects other unrelated phases, and there are the following problems when only the change in each line voltage is detected.

第3図Aは無限大母線電圧系統に単相のリアクトルXL
負荷された場合の回路図を示す。ただし系統の電源イン
ピーダンスの抵抗分は無視している。このときの各相電
圧の関係を同B図に示す。電圧検出器81では線間電圧を
検出しており、u−v間ではVsu−vからVu−vまで変
動することになり、v−w,w−u間についても同様に変
化する。
Figure 3 A shows a circuit diagram of a case where a single-phase reactor X L is loaded in the infinite bus voltage system. However, the resistance component of the power supply impedance of the system is ignored. The relationship between the phase voltages at this time is shown in FIG. The voltage detector 81 detects the line voltage, which changes from Vsu-v to Vu-v between u and v, and also changes between vw and wu.

ところが、このような単相リアクトル負荷が突発的に生
じ、それによる変動を可及的すみやかに抑制する場合を
考えると、u−v間,v−w間、w−u間ともに電圧が降
下しているため、各相制御回路はリアクトル電流をしぼ
り込み、電圧を上昇させようと機能する。現実にはu−
v間リアクトルのみ動作すればよいところが、各相全て
動作し、互に干渉しながら変動抑制することになるた
め、目標値に到達するには時間がかかってしまう。
However, considering the case where such a single-phase reactor load suddenly occurs and the fluctuation due to it is suppressed as quickly as possible, the voltage drops between uv, vw, and wu. Therefore, each phase control circuit functions to squeeze the reactor current and increase the voltage. U-
Although it is sufficient to operate only the reactor between v, all the phases operate and the fluctuations are suppressed while interfering with each other, so it takes time to reach the target value.

もちろん従来の回路構成によっても最終的には変動を抑
制した状態に落着くのであるが、突発的な変動に対して
速応することは困難である。
Of course, the conventional circuit configuration will eventually settle in a state in which fluctuations are suppressed, but it is difficult to quickly respond to sudden fluctuations.

〔発明の開示〕[Disclosure of Invention]

本発明は前記突発的に不平衡且つ急峻に負荷が変動した
場合に速応して電圧変動を抑制できるように、不平衡負
荷による電圧の不平衡を検出し、消費する無効電力を変
化させて不平衡を抑制する回路において、一つの線間電
圧変動を形成する2つの相電圧変動の和に、残る一つの
相電圧変動の差をとった値を、対応する線間の制御信号
とし、各相間で互に干渉を受けずに独立に電圧変動抑制
のできる情報に変換し、各線間無効電力の制御に利用す
ることのできる不平衡電圧検出装置を備える電圧変動抑
制装置にある。
The present invention detects the voltage imbalance due to the unbalanced load and changes the reactive power consumed so that the voltage fluctuation can be suppressed in a quick response when the load suddenly changes unbalanced and sharply changes. In a circuit that suppresses imbalance, the sum of the two phase voltage fluctuations that form one line voltage fluctuation and the difference between the remaining one phase voltage fluctuations is taken as the control signal between the corresponding lines. The voltage fluctuation suppressing device includes an unbalanced voltage detecting device that can be independently converted into information that can suppress voltage fluctuations without being interfered with each other and can be used for controlling each line reactive power.

以下、本発明において使用されるサイリスタ制御装置を
第4図により説明する。
Hereinafter, the thyristor control device used in the present invention will be described with reference to FIG.

まず母線3より、PTにて各相電圧を計測し、各電圧検出
器81にて直流に変換し、Vu,Vv,Vwを得る。
First, from the bus bar 3, each phase voltage is measured by PT and converted into direct current by each voltage detector 81 to obtain Vu, Vv, Vw.

次に設定値Vrefと減算器82において比較し、各相電圧変
動△Vu,△Vv,△Vwを求め、次の(1)式で示すように各
加減算器85に入力して演算を行う。
Next, the set value Vref is compared with the subtractor 82 to obtain each phase voltage fluctuation ΔVu, ΔVv, ΔVw, which is input to each adder / subtractor 85 as shown in the following equation (1) to perform an operation.

このΔVU−v,ΔVV−w,ΔVW−uは、それぞれ電圧変動の
和をとった相の線間の無効電力の制御信号として第1図
のそれぞれの調節器83から入力して、サイリスタスイッ
チ5を制御し、各リアクトル4の通電電流を個々に制御
し、消費無効電力を制御する。
These ΔV U −v, ΔV V −w, and ΔV W −u are input from the respective regulators 83 of FIG. 1 as control signals of the reactive power between the lines of the phases obtained by summing the voltage fluctuations. The thyristor switch 5 is controlled, the energization current of each reactor 4 is individually controlled, and reactive power consumption is controlled.

上記(1)式は3相不平衡時における各相間における干
渉分を除去した変動検出値に当るから、後述のようにこ
の検出値により、各相相互干渉せず、各相独立に目標値
に到達させるものであり、極めて迅速に目標値に到達さ
せることができる。
Since the above formula (1) corresponds to the fluctuation detection value obtained by removing the interference component between the respective phases when the three phases are unbalanced, the detection values do not cause mutual interference of the respective phases and set the target values independently of each other as will be described later. The target value can be reached extremely quickly.

〔動作,効果〕[Operation, effect]

第3図の例について考察してみると、 △Vw=0 ただし|Vs|=|Vsu|=|Vsv|=|Vsw| 従って すなわち、u−v間にのみ電圧変動が検出され、v−w
間,w−u間には電圧変動は検出されない。この信号によ
り、u−v間のみ電圧を上昇させるように、リアクトル
に制御が加えられ、v−w,w−u間リアクトルには制御
動作を必要としないことになり、単相負荷に対して、他
相からの干渉を受けず、適確かつ高速の制御を行うこと
ができる。以上は変動負荷が単相のリアクトルの例で述
べたが、いかなる不平衡負荷においても、同様の対応が
できることはいうまでもない。
Considering the example in FIG. 3, △ Vw = 0 However, | Vs | = | Vsu | = | Vsv | = | Vsw | That is, the voltage fluctuation is detected only between uv and v-w.
Voltage fluctuations are not detected during the interval between w and u. By this signal, the reactor is controlled so as to increase the voltage only between u and v, and the reactor between vw and wu does not require a control operation, so that the single phase load It is possible to perform proper and high-speed control without receiving interference from other phases. In the above, the example of the reactor in which the fluctuating load is a single phase has been described, but it goes without saying that the same measure can be applied to any unbalanced load.

もし電圧変動を発生させている負荷の電流が計測できる
ならば、負荷の無効電力を検出し、その出力信号を第1
図の調節器83の出力に加算してリアクトルを制御すれ
ば、上記無効電力検出制御の残留電圧変動分が本発明の
制御系で修正されるような方向に動く。
If the current of the load causing the voltage fluctuation can be measured, the reactive power of the load is detected and its output signal is
If the reactor is controlled by adding it to the output of the regulator 83 in the figure, the residual voltage fluctuation in the reactive power detection control moves in such a direction as to be corrected by the control system of the present invention.

以上説明したように、突発的に生じた電圧変動を迅速に
抑制することができる。
As described above, it is possible to quickly suppress sudden voltage fluctuations.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明が適用される電圧抑制装置の一例を示
す。 第2図は直列リアクトルとサイリスタスイッチによる無
効電流回路の詳細図である。 第3図Aは単相負荷が接続された場合の回路説明図であ
り、同Bは前記の負荷接続があった場合の各相、各相間
の電圧関係の説明図である。 第4図は本発明に使用されるサイリスタ制御装置の例を
示す。 1……無限大母線、2……電源インピーダンス、3……
母線、4……直列リアクトル、5……サイリスタスイッ
チ、6……並列コンデンサ、7……PT、8……制御装
置、81……電圧検出器、82……減算器、83……調節器、
84……パルス発生器、85……加減算器。
FIG. 1 shows an example of a voltage suppression device to which the present invention is applied. FIG. 2 is a detailed diagram of a reactive current circuit including a series reactor and a thyristor switch. FIG. 3A is an explanatory diagram of a circuit when a single-phase load is connected, and FIG. 3B is an explanatory diagram of each phase and a voltage relationship between the phases when the load connection is made. FIG. 4 shows an example of the thyristor control device used in the present invention. 1 ... Infinity bus, 2 ... Power source impedance, 3 ...
Bus bar, 4 ... Series reactor, 5 ... Thyristor switch, 6 ... Parallel capacitor, 7 ... PT, 8 ... Control device, 81 ... Voltage detector, 82 ... Subtractor, 83 ... Regulator,
84 …… Pulse generator, 85 …… Adder / subtractor.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】不平衡負荷による電圧の不平衡を検出し、
消費する無効電力を変化させて、前記不平衡を制御する
回路において、一つの線間電圧の変動を形成する2つの
相電圧変動の和に、残る一つの相電圧変動の差をとった
値を前記和をとった相の線間の無効電力の制御信号とし
て用いることを特徴とする電圧変動抑制装置。
1. An unbalanced voltage due to an unbalanced load is detected,
In the circuit for controlling the imbalance by changing the consumed reactive power, the sum of the two phase voltage fluctuations forming one line voltage fluctuation is taken as the difference between the remaining one phase voltage fluctuations. A voltage fluctuation suppressing device which is used as a control signal for reactive power between lines of the summed phases.
JP58059582A 1983-04-04 1983-04-04 Voltage fluctuation suppression device Expired - Lifetime JPH07101973B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58059582A JPH07101973B2 (en) 1983-04-04 1983-04-04 Voltage fluctuation suppression device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58059582A JPH07101973B2 (en) 1983-04-04 1983-04-04 Voltage fluctuation suppression device

Publications (2)

Publication Number Publication Date
JPS59185124A JPS59185124A (en) 1984-10-20
JPH07101973B2 true JPH07101973B2 (en) 1995-11-01

Family

ID=13117358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58059582A Expired - Lifetime JPH07101973B2 (en) 1983-04-04 1983-04-04 Voltage fluctuation suppression device

Country Status (1)

Country Link
JP (1) JPH07101973B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532104A (en) * 1978-08-29 1980-03-06 Toshiba Corp Method and apparatus for speed control in intermittent load operation

Also Published As

Publication number Publication date
JPS59185124A (en) 1984-10-20

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