JPH0712055B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0712055B2 JPH0712055B2 JP62274730A JP27473087A JPH0712055B2 JP H0712055 B2 JPH0712055 B2 JP H0712055B2 JP 62274730 A JP62274730 A JP 62274730A JP 27473087 A JP27473087 A JP 27473087A JP H0712055 B2 JPH0712055 B2 JP H0712055B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- buried layer
- semiconductor device
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に選択エピタ
キシャル成長技術を用いて形成したエピタキシャル領域
内に能動素子を形成する半導体装置に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device in which an active element is formed in an epitaxial region formed using a selective epitaxial growth technique.
従来、この種の半導体装置においては、成長させるエピ
タキシャル領域に高濃度埋込領域を必要とする場合に
は、この埋込領域を囲むようにして開孔部を形成した上
で、この開孔内に選択エピタキシャル層を成長させる方
法がとられている。Conventionally, in this type of semiconductor device, when a high-concentration buried region is required for an epitaxial region to be grown, an opening portion is formed so as to surround the buried region, and then the selected inside of the opening is selected. The method of growing an epitaxial layer is taken.
例えば、第4図(a)乃至(c)はその一例を工程順に
示す断面図である。For example, FIGS. 4A to 4C are sectional views showing an example thereof in the order of steps.
即ち、第4図(a)はシリコン基板1上に砒素の埋込層
2を形成し、950℃の高圧酸化により酸化膜3を形成し
た状態を示している。ここで、砒素埋込層2は濃度10cm
-3深さ1.5μmであるが、埋込層の無い所で酸化膜が1.5
μmになるように酸化を行うと、埋込層上での酸化膜厚
は1.75μmとなる。このとき、埋込層上の酸化膜は周囲
から約1350Å盛り上がり、かつ埋込層中に周囲より約11
50Å食い込んで段差が発生される。That is, FIG. 4A shows a state in which the buried layer 2 of arsenic is formed on the silicon substrate 1 and the oxide film 3 is formed by high-pressure oxidation at 950 ° C. Here, the arsenic buried layer 2 has a concentration of 10 cm.
-3 The depth is 1.5 μm, but the oxide film is 1.5 where there is no buried layer.
When oxidation is performed so that the thickness becomes μm, the oxide film thickness on the buried layer becomes 1.75 μm. At this time, the oxide film on the buried layer rises from the surroundings by about 1350Å, and in the buried layer, about 11
50 Å It bites and a step is generated.
次に、第4図(b)のように反応性イオンエッチング
(RIE)技術を用いて酸化膜3を選択エッチングし、埋
込領域2を囲む形で選択エピタキシャル層を形成するた
めの領域を開孔する。Next, as shown in FIG. 4B, the oxide film 3 is selectively etched using the reactive ion etching (RIE) technique to open a region for forming a selective epitaxial layer so as to surround the buried region 2. Make a hole.
次いで、露出したシリコン基板の表面を適切な方法で清
浄にした後、第4図(c)のように選択エピタキシャル
層4を成長する。この選択エピタキシャル成長は、シリ
コンと酸化シリコンの領域を有する基板にエピタキシャ
ル層を形成するとき、SiH4系のガスとHClの流量比を適
切に選ぶことにより、酸化シリコン表面にはシリコン層
を成長させないでシリコン表面だけシリコンのエピタキ
シャル層を成長させようとする技術で、その代表的な成
長条件は、温度950℃,圧力50Torr,SiHCl2の流量300SCC
M HClの流量1100SCCM,H2の流量170SCMである。成長速度
は約0.1μm/minなので、15分成長することにより、選択
エピタキシャル層の表面と酸化膜の表面を一致させるこ
とができる。Then, after the exposed surface of the silicon substrate is cleaned by an appropriate method, the selective epitaxial layer 4 is grown as shown in FIG. 4 (c). In this selective epitaxial growth, when an epitaxial layer is formed on a substrate having regions of silicon and silicon oxide, a silicon layer is not grown on the surface of silicon oxide by appropriately selecting the flow rate ratio of SiH 4 system gas and HCl. This is a technology for growing an epitaxial layer of silicon only on the silicon surface. Typical growth conditions are: temperature 950 ° C, pressure 50 Torr, SiHCl 2 flow rate 300SCC.
The flow rate of M HCl is 1100 SCCM and the flow rate of H 2 is 170 SCM. Since the growth rate is about 0.1 μm / min, the surface of the selective epitaxial layer and the surface of the oxide film can be made to coincide with each other by growing for 15 minutes.
しかしながら、上述した従来の構造では、シリコンエピ
タキシャル成長領域内に存在する砒素埋込層2の境界箇
所には酸化膜3の形成時に生じた1150Åの段差があるた
め、選択エピタキシャル成長を行うと、第4図(c)の
ように埋込段上のエピタキシャル表面に欠陥Xが生じ
る。この欠陥によりエピタキシャル層に形成される素子
の特性不良が発生し、半導体装置の製造歩留りが低下さ
れるという問題がある。第6図はこの欠陥の発生の様子
を示す表面顕微鏡観察図である。However, in the conventional structure described above, there is a step of 1150Å generated at the time of forming the oxide film 3 at the boundary portion of the arsenic burying layer 2 existing in the silicon epitaxial growth region. As shown in (c), a defect X occurs on the epitaxial surface on the buried step. This defect causes a characteristic defect of the element formed in the epitaxial layer, which causes a problem that the manufacturing yield of the semiconductor device is reduced. FIG. 6 is a surface microscope observation view showing the appearance of the defects.
本発明は欠陥を生じることなくエピタキシャル層を成長
することが可能な半導体装置の製造方法を提供すること
を目的としている。It is an object of the present invention to provide a method for manufacturing a semiconductor device that can grow an epitaxial layer without causing defects.
本発明の半導体装置の製造方法は、埋込層を有する半導
体基板の表面に熱酸化して酸化膜を形成し、この酸化膜
を埋込層の領域内でしかも酸化膜によって生じる埋込層
表面の段差の範囲内で開孔して埋込層の表面を露呈さ
せ、更に開孔内の埋込層の露呈された表面に選択エピタ
キシャル成長法によりエピタキシャル層を成長する工程
を含んでいる。According to the method of manufacturing a semiconductor device of the present invention, an oxide film is formed by thermally oxidizing the surface of a semiconductor substrate having a buried layer, and the oxide film is formed in the buried layer region and by the oxide film. The step of opening a hole within the range of the step to expose the surface of the buried layer, and further growing an epitaxial layer on the exposed surface of the buried layer in the hole by a selective epitaxial growth method.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図であり、その製造方
法を第2図(a)及び(b)に示している。FIG. 1 is a sectional view of an embodiment of the present invention, and its manufacturing method is shown in FIGS. 2 (a) and 2 (b).
第1図に示すように、この半導体装置はシリコン基板1
に砒素埋込層2を形成し、この上にN型エピタキシャル
層4を成長しかつその周囲を酸化膜3で包囲した構成と
している。このエピタキシャル層4内には図外の素子が
形成される。また、ここではエピタキシャル層4は埋込
層2よりも平面寸法を小さくし、埋込層2の領域内にの
み成長されるように構成している。As shown in FIG. 1, this semiconductor device has a silicon substrate 1
An arsenic burying layer 2 is formed on the substrate, an N type epitaxial layer 4 is grown on the arsenic burying layer 2, and the periphery thereof is surrounded by an oxide film 3. An element (not shown) is formed in the epitaxial layer 4. Further, here, the epitaxial layer 4 has a plane dimension smaller than that of the buried layer 2 and is configured to grow only in the region of the buried layer 2.
先ず、第2図(a)はシリコン基板1の表面に砒素埋込
層2を形成し、この埋込層上に1.75μmの酸化膜3を形
成した状態を示している。埋込層2の周辺に酸化膜の食
い込みによる1150Åの段差がシリコン表面に見られる。First, FIG. 2 (a) shows a state in which an arsenic burying layer 2 is formed on the surface of a silicon substrate 1 and an oxide film 3 of 1.75 μm is formed on this burying layer. A step of 1150 Å due to the oxide film biting is seen on the silicon surface around the buried layer 2.
そして、この酸化膜3に対してRIE法により選択エッチ
ングを行ってエピタキシャル成長のための開孔部を開設
するが、このとき開孔部は第2図(b)に示すように、
前記埋込層2よりも小さくなるようにする。換言すれば
埋込層2の領域内に開孔部が開設されるように選択エッ
チングを行う。Then, selective etching is performed on this oxide film 3 by the RIE method to open an opening for epitaxial growth. At this time, the opening is formed as shown in FIG. 2 (b).
It is made smaller than the buried layer 2. In other words, the selective etching is performed so that the openings are formed in the region of the buried layer 2.
しかる上で、この開孔部内に選択エピタキシャル成長を
行い、エピタキシャル層4を形成することにより、第1
図の構成が完成される。Then, selective epitaxial growth is carried out in this opening to form the epitaxial layer 4, so that the first
The structure of the figure is completed.
この構成によれば、埋込層2を形成したことにより酸化
膜3形成時に埋込層2に生じる段差がエピタキシャル層
4の領域内に入ることがない。このため、エピタキシャ
ル成長時に欠陥が生じることがなく、エピタキシャル層
4内に形成する素子の特性不良の発生を防止し、半導体
装置の歩留りを向上できる。According to this structure, the step formed in the buried layer 2 when the oxide film 3 is formed by forming the buried layer 2 does not enter the region of the epitaxial layer 4. Therefore, no defects are generated during the epitaxial growth, the characteristic defects of the elements formed in the epitaxial layer 4 can be prevented, and the yield of the semiconductor device can be improved.
第3図は本発明を応用した例の縦断面図である。ここで
は同一砒素埋込層2上に複数個のN型シリコン選択エピ
タキシャル領域4a,4b,〜4nを有する例を示しており、全
ての選択エピタキシャル領域4a,4b,〜4nが砒素埋込層2
の領域内に位置するため、各選択エピタキシャル層4a,4
b,〜4nに欠陥が発生することはない。第5図はこの例の
表面顕微鏡観察図であり、欠陥が生じていないことが判
る。FIG. 3 is a vertical sectional view of an example to which the present invention is applied. Here, an example is shown in which a plurality of N-type silicon selective epitaxial regions 4a, 4b, to 4n are provided on the same arsenic buried layer 2, and all the selective epitaxial regions 4a, 4b, to 4n are arranged in the arsenic buried layer 2.
Of the selective epitaxial layers 4a, 4
No defects occur in b, ~ 4n. FIG. 5 is a surface microscopic observation view of this example, and it can be seen that no defect has occurred.
なお、本発明は高濃度ボロン埋込層の上にP型選択エピ
タキシャル層を形成する構成においても同様に適用する
ことができる。The present invention can be similarly applied to the structure in which the P-type selective epitaxial layer is formed on the high-concentration boron burying layer.
以上説明したように本発明は、半導体基板に形成した酸
化膜を埋込層の領域内で開孔してエピタキシャル層を形
成した工程を含んでいるので、酸化膜を熱酸化法で形成
することで埋込層に段差が生じるようなことがあって
も、選択エピタキシャル領域内に埋込層の段差が存在す
ることはなく、欠陥ないエピタキシャル層を形成して素
子の特性不良を防止でき、かつ半導体装置の製造歩留り
を向上できるという効果がある。As described above, the present invention includes a step of forming an epitaxial layer by opening an oxide film formed on a semiconductor substrate in a region of a buried layer, so that the oxide film can be formed by a thermal oxidation method. Even if there is a step in the buried layer due to, the step of the buried layer does not exist in the selective epitaxial region, a defect-free epitaxial layer can be formed, and defective characteristics of the element can be prevented, and There is an effect that the manufacturing yield of semiconductor devices can be improved.
第1図は本発明にかかる半導体装置の一実施例の断面
図、第2図(a)及び(b)はその製造方法を工程順に
示す断面図、第3図は本発明の他の実施例の断面図、第
4図(a)乃至(c)は従来構造を製造工程順に示す断
面図、第5図は本発明の半導体装置の顕微鏡観察図、第
6図は従来の半導体装置の顕微鏡観察図である。 1……シリコン基板、2……埋込層、3……酸化膜、4,
4a,4b,〜4n……エピタキシャル層。FIG. 1 is a sectional view of an embodiment of a semiconductor device according to the present invention, FIGS. 2 (a) and 2 (b) are sectional views showing the manufacturing method in the order of steps, and FIG. 3 is another embodiment of the present invention. 4A to 4C are sectional views showing a conventional structure in the order of manufacturing steps, FIG. 5 is a microscope observation view of a semiconductor device of the present invention, and FIG. 6 is a microscope observation of a conventional semiconductor device. It is a figure. 1 ... Silicon substrate, 2 ... Buried layer, 3 ... Oxide film, 4,
4a, 4b, ~ 4n ... Epitaxial layers.
Claims (1)
を有し、この酸化膜には前記埋込層上に開孔を有し、こ
の開孔内にエピタキシャル層が形成されてなる半導体装
置の製造方法において、前記酸化膜を前記半導体基板の
表面を熱酸化して形成する工程と、前記酸化膜を前記埋
込層の領域内でしかも前記酸化膜によって生じる埋込層
表面の段差の範囲内で開孔して前記埋込層の表面を露呈
させる工程と、前記開孔内の前記埋込層の露呈された表
面に選択エピタキシャル成長法によりエピタキシャル層
を成長する工程を含むことを特徴とする半導体装置の製
造方法。1. A semiconductor substrate having a buried layer has an oxide film on a surface thereof, and the oxide film has an opening on the buried layer, and an epitaxial layer is formed in the opening. In the method of manufacturing a semiconductor device, the step of forming the oxide film by thermally oxidizing the surface of the semiconductor substrate, and the step of the oxide film in the region of the buried layer and on the surface of the buried layer caused by the oxide film. And exposing the surface of the buried layer within the range, and growing an epitaxial layer on the exposed surface of the buried layer in the opening by a selective epitaxial growth method. And a method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62274730A JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62274730A JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01119038A JPH01119038A (en) | 1989-05-11 |
| JPH0712055B2 true JPH0712055B2 (en) | 1995-02-08 |
Family
ID=17545776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62274730A Expired - Lifetime JPH0712055B2 (en) | 1987-10-31 | 1987-10-31 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0712055B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453396A (en) * | 1994-05-31 | 1995-09-26 | Micron Technology, Inc. | Sub-micron diffusion area isolation with SI-SEG for a DRAM array |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5115489A (en) * | 1974-07-29 | 1976-02-06 | Hitachi Ltd | |
| JPS51112277A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device and its production method |
-
1987
- 1987-10-31 JP JP62274730A patent/JPH0712055B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01119038A (en) | 1989-05-11 |
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