JPH07122837B2 - Clock switching control method - Google Patents

Description

The present invention relates to a clock switching control method that prevents generation of logic whiskers at the time of switching clocks, and does not generate logic whiskers in an output clock signal when switching and outputting a plurality of clocks. Data synchronized with the write signal in the clock switching control method that selects and outputs one clock from the external clock of its own system / another system for the purpose of preventing malfunction in the system to which the output clock signal is supplied. Signal or a control signal for outputting a control signal for instructing to select the own system external clock according to the level of an alarm signal for notifying the state change of the external clock and a control signal for instructing to select the other system external clock It has a means to generate other system control signals, and outputs the external clock and other external clocks. At the same time, it has a synchronization clock generating means that detects a period when it is at a low level and outputs a signal notifying the period, and outputs the signal output from the own system or another system control signal generating means and the synchronization clock generating means. It has a configuration as a clock switching control system characterized in that it has a self-system or other-system switching synchronizing means for receiving a signal and outputting a switching signal to the clock switching means.

[Industrial application field]

The present invention relates to a clock switching control system for preventing the occurrence of logic whiskers when switching clocks.

[Conventional technology]

Since reliability is required for data communication, there is a tendency for each device to have a duplicated configuration, but the clock circuit in the device for interfacing with such a duplicated system is selected from multiple external clock signals. If the external clock signal in use is cut off due to a cable disconnection of the clock signal line, etc., immediately switch the other external clock signals to select and operate. , It prevents the occurrence of a stop state in the clock circuit.

It is desired that such a clock switching control system does not generate a logic whisker in the output clock signal at the time of switching.

FIG. 4 shows a conventional clock switching control system. FIG. 4 shows a case in which one clock signal is output by selecting from two systems of external clock signals. The external clock signal being output and the control signal related thereto are shown with their own systems and output. The external clock signal and the control signal related thereto, which are not performed, are shown with other systems attached. A switching circuit 11 is an AND circuit 11
₁ , 11 ₂ .OR circuit 11 ₃ . Reference numeral 12 is a clock switching control circuit that generates a selection signal for clock switching, 13 is a system clock circuit, and 14 is a control unit for controlling the operations of the clock switching control circuit 12 and the clock circuit 13.

The switching circuit 11 selects either the own system external clock signal or the other system external clock signal according to the selection signal given from the clock switching control circuit 12 and supplies the selected clock signal to the clock circuit 13, and the clock circuit 13 uses this. Operate.

The control unit 14 switches the external clock signal when the own system alarm signal or the other system alarm signal is given through the clock switching control circuit 12 and when it is related to the clock signal currently in use. It decides what should be done and outputs a clock switching operation start signal to the clock switching control circuit 12, whereby the clock switching control circuit 12 outputs a selection signal to the switching circuit 11 and the external clock signal in use. To another external clock signal.

In the conventional clock switching control method, when an own system alarm signal or another system alarm signal is generated, the external clock signal is immediately switched without recognizing the states of the own system external clock signal and the other system clock signal, System of selected clock signal (clock circuit etc.)
It was configured to feed and operate.

However, when a plurality of clock signals are switched in the switching circuit 11, a logic whisker may be generated in the output clock signal. However, if such a clock signal is supplied to the system (clock circuit etc.), malfunction may occur. There is a problem that it occurs.

[Problems to be Solved by the Invention]

The present invention is intended to solve the above-mentioned problems of the prior art, and when switching and outputting a plurality of clock signals, a logic whisker is not generated in the output clock signals. It is an object of the present invention to provide a clock switching control method that does not cause a malfunction in a supplied system (clock circuit or the like).

[Means for Solving the Problems]

The present invention, as shown in the principle configuration of FIG. 1, selects and outputs one clock signal from a plurality of external clock signals, and outputs another clock signal by inputting a control signal corresponding to the external clock signal being output. A clock switching control system for selecting and outputting an external clock signal is provided with a synchronizing clock generating means 1, a switching synchronizing means 2, and a clock switching means 3. Here, the synchronizing clock generating means 1 detects a period in which the external clock signal being output and another external clock signal are simultaneously at a low level and generates an output.

The switching synchronization means 2 generates a selection signal in synchronization with the output of the synchronization clock generation means 1 when a control signal corresponding to the external clock signal being output is generated.

The clock switching unit 3 selects and outputs another external clock signal instead of the external clock signal being output in response to the selection signal from the switching synchronization unit 2.

Therefore, the structure of the present invention is as follows. That is,
The present invention relates to a clock switching control method for selecting and outputting one clock from an external clock of its own system / another system, and using the level of an alarm signal for notifying a change in the state of a data signal or an external clock synchronized with a write signal. It has an own system control signal generating means for outputting a control signal for instructing to select an external clock and another system control signal generating means for outputting a control signal for instructing to select another system external clock. It has a synchronizing clock generating means for detecting a period in which it is simultaneously at a low level with another external clock and outputting a signal notifying the period, and the signal and synchronizing clock output from the own system or another system control signal generating means. Synchronous switching of own system or other system that receives the signal output from the generation means and outputs the switching signal to the clock switching means Having the configuration as a clock switching control method characterized by having a step.

[Action]

The synchronized clock generation means 1 detects the period in which the external clock signal being output (the external clock signal of its own system) and the external clock signal not being output (the external clock signal of the other system) are at the low level at the same time, and outputs the output. Occur.

When a control signal for the external clock signal being output is generated, a corresponding switching synchronization means 2 generates a clock switching selection signal in synchronization with the output of the synchronization clock generation means 1.

The clock switching means 3 performs a switching operation so as to select and output another external clock signal instead of the external clock signal being output in response to the selection signal from the switching synchronization means 2.

In this way, when one clock signal is selected and output from multiple external clock signals, and when another external clock signal is selected and output by the input of the control signal corresponding to the external clock signal being output, the output The state of the external clock signal inside and the external clock signal that is not output is monitored, and the switching operation is performed while both external clock signals are at the low level. To be prevented.

〔Example〕

FIG. 2 is a block diagram of a clock switching control system as an embodiment of the present invention, in which the corresponding parts in FIG. 1 are indicated by the same numbers, 2A is a self-switching synchronous circuit, and 2B is The other system switching synchronization circuit, 8A is its own control signal generator, and 8B is another system control signal generator. In the synchronization clock generating circuit 1, 1 ₁ to 1 ₄ are AND circuits,
1 ₅ is an OR circuit. Autologous switching synchronous circuit 2A, in another system switching synchronous circuit 2B, 2 ₁ to 2 ₃ is the register, the 2 ₄ is an inverter. In the clock switching circuit 3, 3 ₁
~ 3 ₄ is an AND circuit, and 3 ₅ is an OR circuit. In the own system control signal generator 8A and the other system control signal generator 8B, 8 ₁ and 8 ₂ are OR circuits, and 8 ₃ is an AND circuit.

Further, FIG. 3 is a time chart showing signals of respective parts in the embodiment of FIG. 2, wherein is an internal clock signal and is a system clock synchronized with the internal clock signal.
Phase clock signal, the self-system external clock signal, the other-system external clock signal, the own system alarm signal, the output signal of the synchronization clock generating circuit 1, the register 2 ₁ Q output, the register 2 ₂ Q output , the Q output of the register 2 _3, is the output clock signal of the clock switching circuit 3.

In the synchronization clock generating circuit 1, normally an AND circuit 1 _3, 1 ₄ and OR circuit 1 _5, corresponding to the period in which autologous external clock signal and another system external clock signal are both low level, the output signal Is occurring.

When a situation occurs where the output clock signal of the clock switching circuit 3 should be switched from the own system external clock signal to the other system external clock signal, the own system alarm signal becomes high level in the own system control signal generator 8A.

Thus the own system switching synchronous circuit 2A, the data input D is given via the OR circuit _82, OR circuit _81, via the AND circuit 8 ₃ by the clock input CK is supplied in synchronization with the I-phase clock signal produce read output signal to the register 2 ₁ Te, the output signal in synchronization with the internal clock signal applied through the inverter 2 register
Resulting output signal by being read into 2 _2, the output signal produces the output signal by being read into the register 2 ₃ in synchronism with the output signal of the synchronization clock generating circuit 1.

In the clock switching circuit 3, the AND circuits 3 ₁ and 3 ₂ turn on the AND circuit 3 ₄ on condition that the output signal is not generated from the register 2 ₃ in the other system switching synchronization circuit 2B. This other system external clock signal is outputted through the OR circuit ₃₅ as an output clock signal.

Switching of the output clock signal can also be performed by software. In this case, the system control signal generator 8A
By giving the write signal and the data at
OR signal 8 _1, 8 _2, read in the same manner as the register 2 ₁ via the AND circuit 8 ₃ is performed, in the same manner as above description, the switching of the output clock signal is performed following.

〔The invention's effect〕

As described above, according to the present invention, when an output clock signal is generated by selecting from a plurality of external clock signals,
Since the state of the external clock signal being output and the state of the external clock signal not being output is monitored and the switching operation is performed while both external clock signals are at the low level, a logic whisker is generated in the output clock signal at the time of switching. Therefore, it is possible to prevent malfunction in a system (clock circuit or the like) that operates by being supplied with the output clock signal.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a clock switching control system of the present invention, FIG. 2 is a diagram showing a block configuration of a clock switching control system as an embodiment of the present invention, and FIG. 3 is a block diagram of FIG. FIG. 4 is a time chart diagram showing signals of respective parts in the embodiment, and FIG. 4 is a diagram showing a conventional clock switching control system. 1 ... Synchronized clock generation circuit (means) 1 ₁ to 1 ₄ , 3 _{1 to} 3 ₄ , 8 ₃ , 11 ₁ , 11 ₂ ... AND circuit 1 ₅ , 3 ₅ , 8 ₁ , 8 ₂ , 11 ₃ ... … Or circuit 2 …… Switching synchronization means 2A …… Self switching synchronization circuit 2B …… Other system switching synchronization circuit 2 ₁ to 2 ₃ …… Register 2 ₄ …… Inverter 3 …… Clock switching circuit (means) 8A …… Own system control signal generator 8B …… Other system control signal generator 11 …… Switching circuit 12 …… Clock switching control circuit 13 …… Clock circuit 14 …… Control unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoichi Kawahara 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Daiichi Communication Software Co., Ltd. (72) Inventor Rento Nakano Kohoku, Yokohama-shi, Kanagawa 3-9-18 Shin-Yokohama, Fujitsu 1st Communication Software Co., Ltd. (72) Inventor Tatsuji Hamamura 3-9-18 Shinyokohama, Kohoku-ku, Yokohama-shi Kanagawa (72) Invention Shigeaki Kawamata, 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa FUJITSU DAIICHI COMMUNICATION SOFTWARE CORPORATION (56) References JP-A-63-245510 (JP, A) JP-A-59-231668 (JP, A) JP-A-56-122297 (JP, A)

Claims (1)

[Claims] 1. In a clock switching control system for selecting and outputting one clock from an external clock of its own system / another system, a self-system is selected according to the level of a data signal synchronized with a write signal or an alarm signal level for notifying a change in the state of the external clock. An external clock being output, which has its own system control signal generating means for outputting a control signal instructing to select the system external clock and another system control signal generating means for outputting a control signal instructing to select the other system external clock. And the other external clock simultaneously detect a period in which it is at a low level, and have a synchronization clock generating means for outputting a signal notifying the period, and the signal output from the own system or another system control signal generating means and the synchronization A switching system that outputs the switching signal to the clock switching means by receiving the signal output from the clock generating means Clock switching control method, characterized by having means.