JPH0720170B2 - Interface device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems Action Example I. Correspondence between Example and FIG. II. Configuration of Embodiment III. Operation of Embodiment (i) Overall Operation (ii) When PCM Link Interface Unit Is Not Installed (iii) When All PCM Link Interface Units Are Installed (iii-1 ) No data failure (iii-2) Data failure (iv) Clock selection operation (iv -1) All PCM link interface units are installed and no data failure (iv-2) ) When the PCM link interface section is not installed and there is no data failure (iv-3) When there is a data failure (v) When the control section is switched IV. Summary of embodiments V. Modification of invention Effect of the invention [Outline] Based on the data individually input to each of the plurality of link interface means commonly connected to each of the plurality of control means, the main control means in the subsequent stage, according to the failure information of the data and the desired clock, Regarding an interface device capable of deciding which control means is to be activated, for the purpose of enabling normal selection of a desired clock even if the control means is switched, each link interface means is activated. A timing determining unit that obtains an operation timing signal in accordance with the energizing state signal from the control unit, and an onboard information creating unit in accordance with the energizing state signal and the fault presence signal. A selection operation for obtaining a desired clock from the clock signal by the control means based on the mounting information from each link interface means. A clock selection control unit for controlling the operation is included, and the clock selection by each control unit is controlled according to the presence or absence of each link interface unit.

[Industrial application field]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device, and more particularly to an interface device for controlling data synchronized with a clock individually input to each of a plurality of link interface devices commonly connected to each of at least two control devices. It is a thing.

[Conventional technology]

Conventionally, digital interface devices have been widely used in the field of digital exchange. As an example of this digital interface device, as shown in FIG.
The digital interface device 410 may be installed as an input control device of the network device 420 (for example, a digital exchange). Such digital interface device 410 in a plurality of input PCM signal 401 is supplied with the (four input PCM signal 401 _{1-401 4} in this case), each of the input PCM signal 401 is separably digital exchange (not shown) The communication line with can be secured.

FIG. 5 shows details of the digital interface device 410. In both figures, the digital interface unit 410, for example, two of the control unit 411 ₁ and 411 _2, a plurality of PCM link interface unit 413 (here four PC
It is composed of M link interface units 413 _{1 to} 413 ₄ ). Each PCM link interface unit 413 _1,
Corresponding input PCM signals 401 _{1 to} 401 ₄ are individually supplied. Further, each of the two control portions 411 ₁ and 411 _2, four PCM link interface unit 413 _{1 to 413
4} are commonly connected. That is, the control units 411 ₁ and 4
With 11 ₂ of each of which is "duplicated" is the control unit, each of the PCM link interface unit 413 _{1 to 413 4} are those which are "unification".

Here, four PCM link interface unit 413 _{1 to 413}
Each of _4, two control portions 411 ₁ and 411 ₂ of any act signal generation unit 497, a timing pulse generator 499
The timing is selected by the switching selection unit 455 according to the above, and the operation timing pulse is obtained by the timing generation unit 459. PCM
Each of the link interface unit 413 _{1 to 413 4,} with respect to PCM signal data 435 by the fault information insertion section 441 on the basis of the detailed fault information 433 in the failure detection unit 437, housed in a free channel of the PCM on highway (HW) Then PCM signal 43
9 is output and the two control units 411 ₁ and 411 ₂ are notified.

Each switching selection unit 495 of the control unit 411 has a clock extraction unit 43.
According to the extracted clock 429 from 1, one of the clocks extracted by the PCM link interface unit 413 having no fault is selected as the master clock, and the system is operated as the selected clock 493.

Here, the data failure is extracted by the failure extraction unit 481 and notified to the network device 420.

[Problems to be solved by the invention]

By the way, in the above-mentioned conventional method, the control unit 411 operates the system by selecting one of the extracted clocks from the PCM link interface unit 413 having no fault as the master clock. However, the two control units 41
1 ₁ and 411 ₂ are not synchronized with each other. Therefore, PCM
The failure information can be correctly recognized on the side where the link interface unit 413 is synchronized (hereinafter referred to as the act side), but the failure information is recognized on the side not synchronized (hereinafter referred to as the standby side). I cannot recognize it correctly. Therefore, when the system is switched, it is not known which PCM link interface unit 413 the clock should be selected from, and the master clock for operating the system cannot be properly selected. It was

The present invention has been made in view of such a point, and provides an interface device in which the selection of the master clock for operating the system is normally performed even when the system is switched. It is an object.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the interface device of the present invention.

In the figure, the interface device includes a plurality of link interface means 117 and at least two control means 1.
It has 23 and.

The plurality of link interface units 117 are individually supplied with the input data signals 111 representing data synchronized with the clocks, respectively, and extract the clocks in the input data signals 111 input to each to output the clock signal 113. At the same time, if there is a fault in the input data, fault data indicating that there is a fault is added and a data signal 115 is output.

Further, at least two control means 123 are commonly connected to the plurality of link interface means 117, and the clock signal 1 output from each link interface means 117.
13, the data signal 115 is introduced, and the failure information is extracted by extracting the failure based on the plurality of data signals 115.
And a plurality of link interface means
The clock signal 113 introduced from any one of 117 is selected and the desired clock 121 is output.

Thus, an interface device comprising a plurality of link interface means 117 and at least two control means 123 has a fault information 119 and a desired clock 121.
Is supplied to the main control means 125. This main control means 125 is
The control state is determined based on the supplied failure information 119 and the desired clock 121, and which control means 123 is to be activated is determined.

Each of the plurality of link interface means 117 is
The timing determining unit 127 and the mounting information creating unit 133 are included.

The timing determination unit 127 receives the energized state signal and the timing signal from the energized control unit 123 and obtains the operation timing signal in the link interface unit 117.

The mounting information creating unit 133, based on the energized state signal and the timing signal from the energized control unit 123, and the fault presence signal 129 output when there is a fault in the input data, the link interface unit 117. The on-board information 131 indicating whether or not there is a fault and the input data is faulty is output.

Each of the at least two control means 123 described above
A clock selection control unit 135 is included. The clock selection control unit 135 controls the selection operation for obtaining the desired clock 121 from the clock signal 113 by the control unit 123 based on the mounting information 131 from each link interface unit 117.

Therefore, as a whole, each control means 123 is based on the energized state signal from the energized control means 123, the fault presence signal 129 output when there is a fault in the input data, and the presence or absence of the link interface means 117. Is the clock signal
It is configured to control to obtain the desired clock 121 from 113.

[Action]

Each of the plurality of link interface means 117 is
It operates according to the operation timing signal obtained by receiving the urging state signal and the timing signal from the urged control means 123.

The mounting information creating unit 133, based on the energized state signal and the timing signal from the energized control unit 123, and the fault presence signal 129 output when there is a fault in the input data, the link interface unit 117. And the mounting information 131 indicating that there is a failure in the input data.

Based on this mounting information 131, the clock selection control unit 135 of each control means 123 selects the desired clock 12 from the clock signal 113.
Controls the selection behavior to get 1.

In the present invention, the failure information can be correctly recognized even by the control means 123 (standby side) which is not energized, so that the master clock for operating the system is normally selected even when the system is switched. Be done.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of the interface device in one embodiment of the present invention. FIG. 4 shows an application example of the digital interface device.

I. Correspondence between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be described.

The input data signal 111 corresponds to the input PCM signal 401.

The clock signal 113 corresponds to the extraction clock 229.

The data signal 115 corresponds to the PCM signal 239.

The link interface means 117 corresponds to the PCM link interface unit 213.

The fault information 119 corresponds to the fault data from the fault extraction unit 281.

The desired clock 121 corresponds to the master clock.

The control means 123 corresponds to the control unit 211.

The main control means 125 corresponds to the network device 420.

The timing determination unit 127 corresponds to the switching selection unit 255 and the timing generation unit 259.

Failure presence signal 129 corresponds to the fault information 233 _2.

The mounting information 131 corresponds to the package mounting information 265.

The mounting information creation unit 133 corresponds to the switching selection unit 255 and the package mounting information transmission unit 270.

The clock selection control unit 135 corresponds to the pulse monitoring circuit 287, the OR gate 291, and the switching selection unit 295.

The biased control means 123 corresponds to the control unit 211 on the act side.

The non-energized control means 123 corresponds to the standby side control unit 211.

An embodiment of the present invention will be described below on the basis of the above correspondence.

II. Configuration of Embodiment The digital interface device shown in FIG.
It is an application example as described with reference to the drawings. That is, the digital interface device 210 is the network device 4
It is installed as 20 input control devices, and multiple input PCM signals 401 (4 input PCM signals 4) are provided so that a communication line with each separate digital exchange can be secured.
01 _{1 to} 40 _{1 4} ) are supplied.

In FIG. 2, the digital interface device 210
Has two control portions 211 ₁ and 211 ₂ is composed of four PCM link interface unit 213 _{1 to 213 4.}
Here, in order to make the PCM link interface unit 213 “single”, the PCM link interface unit 213 ₁
To 213 ₄ corresponding input PCM signals 401 _{1 to} 401 ₄
Are supplied separately. Further, in order to "duplex" is a control unit with respect to PCM link interface unit 213 _{1 to 213 4,} each of the two control portions 211 ₁ and 211 _2, four PCM link interface unit 213 _{1 to 213 4} are commonly connected.

Four each of the PCM link interface unit 213 _{1 to 213 4,} and operates in synchronization with either of the two control portions 211 ₁ and 211 _2, PCM link interface unit 213 _{1 to 213 4}
Each of the two control units 211 ₁ and 211 ₂ stores detailed failure information in an empty channel (on the highway) of the PCM.
To notify.

The control unit 211 is a PCM link interface unit with no failure
One of the clocks extracted by 213 is selected as the master clock to operate the system.

Each PCM link interface unit 213 has a corresponding input PC
By the M signal 401, PCM signals representing data synchronized with the clocks are individually input.
Each PCM link interface section 213 extracts the clock based on the PCM signal input to the PCM link interface section 213 and outputs the extracted clock 229, and the received clock extraction section 231.
It is determined whether or not there is a fault in the PCM signal, and if there is a fault, fault information 233 (fault information 233 ₁ , 233 ₂ ) is generated and PCM is generated.
Includes a fault detecting unit 237 for outputting the PCM signal data 235 based on the signals, and fault information insertion section 241 outputs a PCM signal 239 ₁ based on the PCM signal data 235 and error information 233 _1.

Moreover, two control unit 211 (control unit 211 _1, 211 ₂₎ act signal 251 supplied from the (act signal 251 _1, 251 ₂₎ and the timing signal 253 (timing signal 253 _1, 253 ₂₎ is supplied, the switching a switching selector 255 to output a respective signal selected, the PCM link interface unit 213 by the selection timing signal 257 in accordance with the said changeover switching selection unit timing signal 253 ₁ or 253 ₂ selected by 255
Each circuit portion of the timing generator 259 for creating a timing signal to the (such as failure detection unit 237), selection activation signal 261 in accordance with the activation signal 251 ₁ or 251 ₂ selected by the switching selecting portion 255, a timing generator timing pulse 263 from section 259, and a package mounting information sending unit 270 for outputting the package mounting information 265 on the basis of the failure information 233 ₂ from the failure detection unit 237.

Here, the package mounting information sending unit 270 includes the inverter 271 whose input side is connected to the operating voltage V _c , and the fault information 2
33 ₂ , an AND gate 273 that takes the logical product of the selection act signal 261 and the timing pulse 263, and an OR gate 2 that takes the logical sum of the output of the inverter 271 and the output of the AND gate 273.
Made with 75 and.

On the other hand, each control unit 211 is commonly connected to the four PCM link interface units 213. The control unit 211 _1, extracts the four disorders outputs four PCM link interface unit 213 _{1 to 213 4} receiving the PCM signal 239 which is introduced into the common from each extraction 4 bits indicating their fault condition the fault information 283 part 281 ₁ ～281 _4, package mounting information introduced from the four PCM link interface unit 213 _{1 to 213 4}
Each of the four pulse monitoring circuits 287 _{1 to} 287 ₄ , which receives 265 in common and monitors their pulse states to output 4-bit mounting monitoring information 285, and the logical sum of the mounting monitoring information 285 and the extracted fault information 283. an OR gate 291 which outputs a clock selection signal 289 taking, selected from the extracted clock 229 to be introduced from the four PCM link interface unit 213 _{1 to 213 4} based on the clock selection signal 289 selects one of the clock clock signals A switching selection unit 295 that supplies 293 to the network device 420 (see FIG. 4), an act signal generation unit 297 that generates an act signal 251, and a timing pulse generation unit 299 that generates a timing signal 253 are included.

III. Operation of Embodiment The operation of the embodiment described above will be described. In the following, the overall operation and the detailed operation will be separately described.

(I) Overall Operation The input PCM signal 401 representing data synchronized with the clock is individually input to each PCM link interface unit 213 of the digital interface device 210. The clock extraction unit 231 that receives this input PCM signal 401 extracts the clock in the input PCM signal 401 and extracts the extracted clock.
It outputs 229. Similarly, the failure detection unit 237 receiving the input PCM signal 401 outputs the data as it is as the PCM signal 239 if there is no failure in the data (bit stream) in the input PCM signal 401, and if there is a failure. and it outputs the detailed fault information as PCM signals 239 ₁ housed in a free channel.

In this way, the digital interface device 210
The extracted clock 229 and the PCM signal 239 obtained from each PCM link interface unit 213 are commonly supplied to the control unit 211 ₁ and the control unit 211 ₂ .

(Ii) PCM link interface unit may now not mounted, it is assumed that PCM link interface unit 213 ₁ is not mounted on the digital interface unit 210.

The PMC link interface unit 213 _1, it means no operating voltage V _c of the package mounting information sending unit 270, package mounting information 265 ₁ is "high" level (open). As a result, when viewed from the control unit 211 side, PCM
It can be seen that link interface unit 213 ₁ is not mounted on the digital interface unit 210.

(Iii) When all PCM link interface units are installed Now, assuming that all four PCM link interface units 213 are installed, the package mounting information sending unit 270 in each PCM link interface unit 213 operates. Since the voltage V _c will be supplied, the output of the inverter 271 is at the “low” level. Thus, package mounting information 265 ₁ to 265 ₄ which are output from all the OR gate 275 of the PCM link interface unit 213 _{1 to 213 4,} the AND gate 273
It depends on the output state of.

Further, it is assumed that the control unit 211 ₁ is on the act side and the control unit 211 ₂ is on the standby side. Therefore, the control unit on the act side
Act signal 251 ₁ from act signal generator 297 in 211 ₁ and timing signal 253 ₁ from timing pulse generator 299 ₁
Doo is selected by the switching selecting portion 255 of the PCM link interface unit 213 _1, the a selection out signal 261 and the selection timing signal 257.

Depending on the selection timing signal 257 thereof is selected, the timing generator 259 provides timing signals to each circuit of the PCM link interface unit 213 _1, package mounting information sending unit 270 generates a timing pulse 263 Supply to. Also, the selected act signal 261
Is also supplied to the AND gate 273 of the package mounting information sending unit 270.

Without (iii-1) data in the input PCM signals 401 ₁ of data failure being input when there is no failure in the PCM link interface unit 213 _1, fault information 233 ₂ from the failure detection unit 237 "low" It is a level. Therefore, the output of the AND gate 273 of the package mounting information sending unit 270 is "low" level, package mounting information 265 ₁ is a "low" level, PCM link interface unit 213 ₁ as viewed from the control unit 211 side It can be seen that is mounted on the digital interface device 210.

On the contrary if there is (iii-2) data to the fault, if any PCM link interface unit 213 fault input PCM signal 401 ₁ of data input to _1, the failure detection unit 237 "high" level Fault information 233 ₂ Occurs. Therefore, the output of the AND gate 273 becomes an output signal depending on the timing pulse 263, and the package mounting information 265 ₁ is in a signal state in which “low” level and “high” level are repeated. Thus, it can be seen that there is a fault in the input PCM signals 401 ₁ of data when viewed from the control unit 211 side PCM link interface unit 213 ₁ is received.

(Iv) Clock selection operation As described above, the PCM link interface unit 213 is installed, the PCM link interface unit 213 is not installed, and the installed PCM is
The notification to the control unit 211 that there is a failure in the input data to the link interface unit 213 is the same in the other PCM link interface units 213. Each control unit 2
Four pulse monitoring circuits 287 in 11 (pulse monitoring circuit 287 ₁
The ～287 ₄₎ each of the four PCM link interface unit 213 (PCM link interface unit 213 _{1 to 213 4)}
Package installation information 265 from (Package installation information 265
_{1 to} 265 ₄ ) are commonly introduced.

FIG. 3 shows a clock selection procedure when all the PCM link interface units 213 are mounted. Hereinafter, FIG. 2 and FIG. 3 will be referred to.

(Iv-1) package mounting information 265 ₁ to package mounting information 265 ₄ from all of the PCM link interface portion is mounted and when there is no fault in the data PCM link interface unit 213 _{1 to 213 4} are all "low" level Is. Further, since there is no fault in the input PCM signals 401 ₁ to 401 _4, extracts fault information 283 (4 bits at the output of the fault extraction part 281 _{1 to 281 4)} from the fault extraction part 281 _{1 to 281 4} is also "low" level Is. Since the clock selection signal 289 output from the OR gate 291 is at “low” level,
Switching selector 295 which receives the clock selection signal 289 selects the extracted clock 229 ₁ based on the priority processing as the selected clock signal 293 (step 311, 312).

(Iv-2) Now if PCM link interface unit is not faulty is and data non mounted, the PCM link interface unit 213 ₁ (b ₀₎ is assumed was not installed, the package mounting information sending unit 270 package mounting information 265 ₁ from is "high" level. In response to this, the pulse monitoring circuit 287 ₁ of the control unit 211
~ Pulse monitoring circuit 287 ₄ outputs a mounting monitoring information 285 to the effect that "PCM link interface unit 213 ₁ is not mounted." Clock selection signal 289 according to the mounting monitoring information 285
Based on, switching selection unit 295 selects the extracted clock 229 ₂ on the basis of the priority processing as the selected clock signal 293.

(Iv-3) Now if there is a failure in the data, if there is an input PCM signal 401 ₁ of data failure being input to the PCM link interface unit 213 _1, the failure detection unit 237 of the PCM link interface unit 213 ₁ " high "level to generate a fault information 233 _2. Accordingly, "low" level corresponding to the package mounting information 265 ₁ timing pulse 263, a "high" level repeatedly signals. In response to this, the pulse monitoring circuits 287 _{1 to} 287 ₄ of the control unit 211 change the "input PCM".
And outputs the loaded monitoring information 285 indicating that the signal 401 ₁ is faulty. "Clock selection signal 289 corresponding to the mounting monitoring information 285
Based on, switching selection unit 295 selects the extracted clock 229 ₂ from the PCM link interface unit 213 ₃ (b ₁₎ as the selected clock signal 293 (step 311,313,314).

Similarly, input PCM signal 401 ₁ and input PCM signal
If there is failure in the 401 _second data, PCM link interface unit 213 ₂ of the fault detection unit 237 also "high" level of the fault information 2
33 ₂ to generate. Thus, package mounting information 265 ₂ also "low" level, a "high" level repeatedly signals, PC
The extracted clock 229 ₃ from the M link interface unit 213 ₃ (b ₂ ) is selected as the selected clock signal 293 (steps 311, 315, 316).

Furthermore, if there is an input PCM signal 401 _1, 401 ₂ and 401 ₃ of the data to the fault, PCM link interface unit 213 ₄ (b ₃₎
Extracted clock 229 ₄ from is selected as the selected clock signal 293 (step 311,313,315,316,318).

Incidentally, if there is a failure in all four input PCM signal 401 _{1-401 4,} a free-running clock (step 319). However, the clock generating means is omitted. Then, it is determined whether or not there is a system switching instruction (step 320). If there is no such instruction (negative determination), the process returns to the first step 311.

(V) When the control unit is switched In the operation described above, the control unit 211 ₁ is on the act side and the control unit 211 ₂ is on the standby side.
It is assumed that the control unit 211 ₂ is switched to the act side and the control unit 211 ₁ is switched to the standby side by the instruction of 0.

That is, after execution of step 319, when it becomes affirmative at step 320, and act side controller 211 ₂ is switched from the control unit 211 ₁ to the control unit 211 _2. In that case, until the PCM signal 239 based on the selected clock signal 293 from the control unit 211 ₂ which becomes the new act side comes, the highway (H
(W) waits for the data to be fetched (step 321) and returns to step 311.

Even in such a case, since the package mounting information 265 _{1 to} 265 ₄ from all the PCM link interface units 213 was also commonly supplied to the control unit 211 ₂ , the control unit immediately after the switching stage. 211 ₂ can perform the operations described above.

As a result, although the two control units 211 ₁ and 211 ₂ are not synchronized with each other, the control unit 211 selects one of the extracted clocks from the PCM link interface unit 213, which has no fault, as the master clock to operate the system. . Therefore, the control unit 211 on the act side and the control unit 2 on the standby side
Even in 11, the fault information can be correctly recognized.
Therefore, when switching from the OUT side to the STANDBY side, the control section 211 on the STANDBY side has the PCM link interface section 2 that has been receiving the clock until now.
13 Selection of the master clock on the basis of the extracted clock 229 ₁ of ₁ is performed normally system operates.

IV. Summary of Examples In this way, all PCM link interface units 2
In the control unit 211 which receives the package mounting information 265 from 13, the pulse monitoring circuit 287 selects the PCM link interface unit 213 mounted on the digital interface unit 210 and the PCM link interface unit 213 which has no fault in the input data and responds accordingly. On-board monitoring information 285
The extraction clock 229 is switched and selected by the switching selection unit 295 based on the (clock selection signal 289) and provided for the master clock.

At this time, since the package mounting information 265 is commonly supplied to all the control units 211, both the act-side control unit 211 and the standby-side control unit 211 can correctly recognize the failure information. Therefore, the selection for the master clock is
Even if you switch from the act side to the standby side,
The system operates normally.

V. Modification of the Invention In the above-described embodiment, the digital interface device 210 is configured with four PCM link interface units 213 and two control units 211. It is not limited to.

Further, although the relationship between the present invention and the above-described embodiment has been described in “I. Correspondence between embodiment and FIG. 1”, the present invention is not limited to this, and various modifications are possible. Can be easily conceived by those skilled in the art.

〔The invention's effect〕

As described above, according to the present invention, in order to operate the system, the fault information is supplied to all the control means, and the presence or absence of the link interface means and the presence or absence of the fault are monitored by each control means. The master clock is normally selected even when the system is switched, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the interface device of the present invention, FIG. 2 is a block diagram of the interface device according to one embodiment of the present invention, and FIG. 3 is an operation of the interface device according to the embodiment of the present invention shown in FIG. FIG. 4 is a configuration diagram showing an application system of a digital interface device, and FIG. 5 is a configuration block diagram showing a conventional interface device. In the figure, 111 is an input data signal, 113 is a clock signal, 115 is a data signal, 117 is a link interface means, 119 is fault information, 121 is a desired clock, 123 is control means, 125 is main control means, and 127 is timing determination. Part, 129 is a fault presence signal,
131 is mounting information, 133 is mounting information creating unit, 135 is a clock selection control unit, 210 and 410 are digital interface devices, 211 and 411 are control units, 213 and 413 are PCM link interface units, 229 and 429 are extracted clocks, 233 and 433 are fault information, and 235 and 435 are PCM. Signal data, 237,437 failure detection unit, 239,439 PCM signal, 241,441 failure information insertion unit, 270
Is the package mounting information sending unit, 281,481 is the failure detection unit, 2
87 is a pulse monitoring circuit, 295 and 495 are switching selection sections, 297 and 497 are act signal generation sections, and 420 is a network device.

Claims (2)

[Claims] 1. Input data signals (111) each representing data synchronized with a clock are individually supplied, and the input data signal (111) input to each is supplied.
Clock signal to extract the clock in (113)
Is output, and if there is a fault in the input data, fault data indicating that there is a fault is added to the data signal (11
5) output multiple link interface means (11
7), the clock signal (113) and the data signal (11) which are commonly connected to the plurality of link interface means (117) and output from each link interface means (117).
5) is introduced, and a fault is extracted based on a plurality of data signals (115) and fault information (119) is output, and at the same time, from any of the plurality of link interface means (117). At least two control means (123) for selecting the introduced clock signal (113) and outputting a desired clock (121), and the fault information (119) and the desired clock (12).
An interface device that supplies the fault information (119) and the desired clock (121) to a main control means (125) that determines a control state based on 1) and determines which control means (123) is to be activated. In the above, each of the plurality of link interface means (117) receives an urging state signal and a timing signal from the urged control means (123) and outputs an operation timing signal in the link interface means (117). A timing determining section (127) for obtaining, an energizing state signal and a timing signal from the energized control means (123), and a fault presence signal (129) output when the input data has a fault. On the basis of the presence or absence of the link interface means (117) and the mounting information (131) indicating that the input data has a failure.
And a mounting information generating unit (133) for outputting the mounting information generating unit (133), wherein each of the at least two control means (123) is based on the mounting information (131) from each link interface means (117). A clock selection control section (13) adapted to control a selection operation for obtaining the desired clock (121) from a clock signal (113) by a clock signal (123).
An interface device including 5), wherein the clock selection by each control means (123) is controlled according to the presence or absence of each link interface means (117). 2. The mounting information (131) comprises a binary signal according to the presence or absence of a link interface means (117) and a binary repeating signal according to the fact that the input data has a fault. The interface device according to claim 1, which is characterized by the above-mentioned.